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USB IP Core USBSS-DEV (formerly named USB3-DEV) USB 3.0 SuperSpeed Device Controller Core

On this page:Description | Features | Applications | Block Diagram | Example Application | Benefits | Support | Deliverables

This IP core implements a device controller that conforms to the USB 3.0 SuperSpeed specification.

SuperSpeed 3.0 USB enables data transfers up to 5 Gbps while also reducing power requirements. It’s use of Sync-N-Go technology reduces user wait-time, and it is backwards-compatible with USB 2.0. The core handles bytes transfer autonomously, and bridges the USB interface to an OCP interface for straightforward system integration (AMBA® AHB and other system interfaces are also available). The USBSS-DEV can be readily customized and optimized for a wide range of specific system applications.

The core is developed for reuse in ASIC and FPGA implementations. The design is strictly synchronous with positive-edge clocking, a synchronous reset and no internal tri-states; therefore scan insertion is straightforward.

Features

• USB 3.0 Specification Rev. 1.0 compliant
• 32-bit OCP Slave interface implemented as a basic microprocessor interface
• Integrated DMA controller with a 32-bit OCP Master Interface
• USB 3.0 PIPE interface to PHY (32-bit)
  
• Control transfers supported by Endpoint 0
  
• Up to 15 IN and 15 OUT configurable/ programmable  endpoints
  
• Synchronous Single Port RAM interface for endpoint buffers
  
• Full Power Management capabilities (U1, U2 & U3 ) with LFPS support
  
• Bulk Stream support
  
• Backwards compatibility achieved through integration with the CAST USB 2.0 (Hi and Full-Speed) Device controller

Applications

The SuperSpeed USB 3.0 device controller core is suitable for a variety of applications, including mass storage products, audio/video systems, communication devices, digital cameras, networking, and digital media controllers.

Block Diagram

Example Application

Here the USBSS-DEV is implemented with internal single-port RAM. The core works as a USB peripheral device, transmitting data between the fast flash memory and PC using the SuperSpeed USB connection. USB data packets are transferred between the on-chip endpoint memory and system memory using an integrated USB protocol-aware DMA controller. The CPU controls the settings of endpoints and services interrupts.

Benefits

• Complete hardware and software solution
• High level of configurability
• Industry standard interfaces that simplify system integration
• Verilog coding style for true technology independence
• Customization to fit user needs
• Flexible licensing schemes

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Deliverables

The core includes everything required for successful implementation:

• HDL RTL source code (soft core) or a post-synthesis EDIF netlist (firm core)
• Extensive SystemC Test Bench that includes: a complete example design, external endpoint buffer, and a USB3.0 device TLM model
• Sophisticated HDL Testbench including external FIFOs, buffers, models of interfaces, and the core
• Simulation script, vectors, and expected results
• Synthesis (soft) or place and route (firm) script
• Comprehensive user documentation, including detailed specifications and a system integration guide

On this page:Description | Features | Applications | Block Diagram | Example Application | Benefits | Support | Deliverables

Download PDF datasheets for more info: Preliminary-ASIC