T8051
Tiny 8051-Compatible 8-Bit Microcontroller IP Core
On this page: Description
| Implementation Results | Features
| Applications | Block Diagram
| Support | Verification
| Deliverables
A semiconductor IP core that implements an extremely small 8-bit microcontroller executing the ASM51 instruction set. It includes peripherals for serial communication, a timer, a multi-purpose I/O port, hardware interrupts, and a JTAG debugger interface.
This 8051 core is based on the fast, configurable CAST R8051XC core (proven in hundreds of successful designs). Sample implementation results show it to require as little as 2,000 ASIC gates for 0.35 um (for the CPU). It achieves this low gate count by sharing resources between several stages of instruction set execution, with careful tuning of instruction cycle latency to reduce hardware resources.
Performance remains high: 4.1 times better than the original Intel™ 8051 as measured by Dhrystone MIPs per MHz. Communication with both built-in and external memories has been accelerated by de-multiplexing the address and data buses, while alternate port functions such as external interrupts and serial interface are available on separate pins.
The T8051 is a microcode-free design developed for reuse in ASIC and FPGA implementations. The design is strictly synchronous with positive-edge clocking, no internal tri-states and a synchronous reset; therefore scan insertion is straightforward. A complete On-Chip Debug Support (OCDS) debugging system compatible with the industry-standard Keil™ µVision Cx51 Development Tools IDE is also available.
See representative implementation results (each
in a new pop-up window):
 
Features
- 100% MCS51® compliant Central Processing Unit
- Extremely small gate count, e.g., TSMC .18 ASIC process:
CPU only = 2.8K
CPU + peripherals = 5.2K (fits in 0.0539 mm2 footprint)
Total, with OCDS debug = 8.5K
- Dummy peripheral replacements for even lower gate count
- Low power consumption
- Fast: performance is 4.1 times classic 8051 (Dhrystone MIPS benchmarks; data available).
- Input/Output port
- Single 8-bit I/O port
- Alternate port functions such as external interrupts and serial interface are separated, providing extra port pins when compared with the standard 8051
- 16-bit Timers/Counter
- Full Duplex Serial Interface
- Serial 1 (80517-like)
- 8-bit UART mode, variable baud rate
- 9-bit UART mode, variable baud rate
- Baud Rate Generator
- Interrupt Controller
- Four Priority Levels with eleven interrupt sources (80C517-like)
- Eight External Interrupts
- Two Low-Level or Falling-Edge Sensitive
- Two Falling-Edge or Rising-Edge Sensitive
- Four Rising-Edge Sensitive
- Internal Data Memory interface
- addresses up to 256 B of Data Memory Space
- External Memory interface
- addresses up to 64 kB of External Program Memory
- addresses up to 64 kB of External Data Memory
- De-multiplexed Address/Data Bus to ease the connection with memories
- Program memory write mode
- On-Chip Special Function Registers interface
- Power Management Unit
- On Chip Debug Support (OCDS)
Applications
This small 8051 microcontroller core is ideal for silicon space-challenged mixed-signal systems (e.g., Zigbee products). It also provides an easily-programmed alternative to hard-coded control logic in many existing applications, and is an excellent choice for low-power and small FPGA-based systems.
Block Diagram
Support
The core as delivered is warranted against defects for ninety days from
purchase. Thirty days of phone and email technical support are included,
starting with the first interaction. Additional maintenance and support
options are available.
Verification
The core has been verified through extensive simulation and rigorous code coverage measurements. All subcomponents were functionally verified with an HDL testbench using their individual test suites. The CPU and ALU have been verified against a proprietary hardware modeler and behavioral models. The test suite for the peripherals has also been developed in their own testbenches, based on either hardware or behavioral models.
The trial ATPG coverage figures met the requirements and reached level of 99%. Additionally the value of IDDQ reached level of 99%.
Deliverables
The core is available in ASIC (synthesizable HDL) and FPGA (netlist)
forms, and includes everything required for successful implementation:
- HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
-
Reference design for proprietary development board
This design uses the T8051 and illustrates how to build and connect memories and port modules
-
Sophisticated HDL Testbench including external FIFOs, buffers, models of interfaces, and the core
-
Simulation script, vectors, expected results, and comparison utility
-
Synthesis (soft) or place and route (firm) script
-
Comprehensive user documentation, including detailed specifications and a system integration guide
On this page: Description
| Implementation Results | Features
| Applications | Block Diagram
| Support | Verification
| Deliverables
Download PDF datasheets for more info: ASIC | Altera | Xilinx
 This core developed by the processor experts at Evatronix
SA
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