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SPI_MS Serial Peripheral Interface Master/Slave Core

On this page: Description | Implementation Results | Features | Applications | Block Diagram | Support | Verification | Deliverables

The Serial Peripheral Interface (SPI) allows high-speed synchronous serial data transfers between microprocessors, microcontrollers and peripheral devices. The SPI_MS core implements the Serial Peripheral Interface, which can operate either as a master or as a slave.

When operating in master mode, the core generates the serial data clock (SCK) and selects the slave device, which will be addressed. When operating in slave mode, another master device generates the serial data clock and activates the slave select input of the core, in order to communicate.

The core was carefully designed to provide the most reliable communication possible, and to achieve very high bit rates.

The SPI_MS is a microcode-free design developed for reuse in ASIC and FPGA implementations. The design is strictly synchronous with positive-edge clocking, no internal tri-states and a synchronous reset; therefore scan insertion is straightforward.

See representative implementation results (each in a new pop-up window):

Features

• Fully synchronous design with one clock domain
• Full duplex, synchronous, 8-bit serial data transfer
• High bit rates
• Master or slave mode
• Bit rates generated in Master mode:
  ÷2, ÷4, ÷8, ÷16, ÷32, ÷64, ÷128, ÷256 of the system clock
• Bit rates supported in Slave mode: f_SCK ‹ =f_SYSCLK ÷2
• Eight Slave Select lines
• MSB first or LSB first data transfer
• Technology independent HDL source code (soft core)
• Optimized netlist for Actel, Altera, Lattice, and Xlinx devices also available (firm core)
  

Applications

The core is suitable for implementing serial interfaces in a wide range of applications, including:

• Embedded microprocessor boards and SOCs
• Consumer and professional audio/video
• Home and automotive radio

Block Diagram

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The core has been verified through extensive simulation and rigorous code coverage measurements.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

• HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
• Sophisticated self-checking Testbench (Verilog versions use Verilog 2001) including external FIFOs, buffers, models of interfaces, and the core
• Simulation script, vectors, expected results, and comparison utility
• Synthesis script (ASICs) or place and route script (FPGAs)
• Comprehensive user documentation, including detailed specifications and a system integration guide

On this page: Description | Implementation Results | Features | Applications | Block Diagram | Support | Verification | Deliverables

Download PDF datasheets for more info: ASIC | Altera | Lattice | Xilinx

 This core developed by the bus interface experts at Alma Technologies S.A