SPDIF-APB Digital Audio Interface Core
On this page: Description
| Features
| Applications | Block
| Deliverables
Implements the Sony/Philips Digital Interface (SPDIF),
a unidirectional and self-clocking interface for connecting digital audio
equipment using linear PCM coded audio samples.
The SPDIF core conforms to the IEC 60958 international standard for
transmitting and receiving fast audio data. This variation includes a
standard bus interface to the AMBA™ APB, making it straightforward
to integrate the SPDIF core with a master system for further processing
of the audio data.
Data collected by the SPDIF-APB is stored in the core’s internal
FIFO, allowing the system to process a relatively slow audio stream in
the interrupt triggered subroutines. The core could also be used for fast
serial non-audio transmission.
The SPDIF-APB is a microcode-free design developed for reuse in ASIC
and FPGA implementations. The design is strictly synchronous with positive-edge
clocking, no internal tri-states and a synchronous reset; therefore scan
insertion is straightforward.
See representative implementation results (each
in a new pop-up window):
Features
- Conforms to the IEC 60958 International Standard
- Programmable: supports both Receiver and Transmitter modes
- Data mode capabilities:
- Supports sample rates from 3kHz to 192kHz (with 98MHz SPDIF system
clock)
- 20/24 bits per sample
- Programmable transmission rate
- Programmable parity bit checking and generation
- Performs master DMA handshake interfacing
- Includes configurable internal FIFO for data streaming, with FIFO
control/status signals
- Power safe capability
- Internal, event stimulated, interrupt request generation, with masking
capability
- Synchronization hold in the under run condition
- Clock recovery from the SPDIF data stream
- Detection of sample rate from the received data stream
- Host processor interface:
- AMBA APB slave unit to interface with the host APB controller, especially
DMA
- Other standard interfaces available
- Other standard processor interfaces available
- Sophisticated self-checking Testbench (Verilog versions use Verilog 2001)
Applications
The core is suitable for implementing a unidirectional, high-speed, digital
audio interface in a variety systems, including:
- CD players
- Digital audio tape (DAT) recorders and players
- Advanced audio encoding/decoding blocks
Block
Deliverables
The core is available in ASIC (synthesizable HDL) and FPGA (netlist)
forms, and includes everything required for successful implementation:
- HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
- An example APB slave design, which uses the SPDIF-APB in a sample
system and shows how to interface with the APB
- Sophisticated self-checking Testbench (Verilog versions use Verilog 2001) including a sample chip design, external
dual-port RAM for the FIFOs, a clock generator, and a set of bus functional
models for APB and SPDIF buses, and a set of comparison units for monitors
the correctness of data sent or received on the SPDIF bus
- A collection of test cases that covers all functionalities of the
core and fulfills strict Code Coverage requirements.
- Scan support insertion scripts
- Simulation script, vectors, expected results, and comparison utility
- Synthesis script (ASICs) or place and route script (FPGAs)
- Comprehensive user documentation, including detailed specifications
and a system integration guide
On this page: Description
| Implementation Results | Features
| Applications | Block
| Deliverables
Download PDF datasheets for more info: ASIC | Altera | Xilinx
This core developed by the bus interface experts at Evatronix
SA
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