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Security IP Core SHA256 256-bit Secure Hash Algorithm Core

On this page: Description | Implementation Results | Applications | Features | Block Diagram | Functional Description | Support | Verification | Export Permits | Deliverables

The SHA256 core is a high-performance implementation of the SHA-256 Secure Hash message digest Algorithm. This one-way hash function conforms to the 1995 US Federal Information Processing Standard (FIPS) 180-2.  It accepts a large, variable-length message and produces a fixed-length message authorization code.

The core is composed of two main modules, the SHA256 Engine Module and the Input Interface Module as shown in the block diagram.  The SHA256 Engine Module applies the SHA256 loops on a single 512-bit message block, while the Input Interface Module performs the message padding.

The processing of one 512-bit block is performed in 66 clock cycles and the bit-rate achieved is 7.75Mbps / MHz on the input of the SHA256 core.

The SHA256 core is equipped with fully-stallable input and output interfaces. These enable the user’s application to stop the input stream according to a data arrival rate, or to stop the output stream when the core is not able to receive data.

The core has been evaluated in a variety of technologies, and is available optimized for ASICs or FPGAs. Representative results show it to produce a competitive implementation, running at 280 MHz and requiring just 20,500 gates in a 0.18 µm ASIC process. The complete deliverables feature comprehensive documentation, and a bit-accurate software model (BAM).

See representative implementation results (each in a new pop-up window):

Applications

The core is suitable for a variety of applications requiring digital signatures or other message origin authentication or tamper protection, including:

• E-commerce
• Data integrity
• Bulk Encryption
• High speed networking equipment
• Secure wireless applications

Features

• Compliant to FIPS 180-2 specification of SHA-256
• 2**64-1 bits maximum message length
• Bit padding
• Supported Message lengths multiple of 8-bits
• Initial values of Chaining Variables selected before synthesis
• 66 processing cycles per message block
• Fully stallable input and output interfaces, ideal for streaming applications
• Optimized design for ASIC or FPGA implementations
• Robust verification environment includes bit-accurate software model
• Scan-ready design architecture

Block Diagram

Functional Description

The input message data is passed in 32-bit words to the core, masked with the input_valid signal. As long as the input_ready signal is active, the external application should keep feeding input data to the core. When the core has received a complete message 512-bit packet, it pauses the input stream, and continues the message processing internally. When the message is processed and the core is ready for the next message, the core permits input data to be fed again. On the final message block, when the last 32-bit word is written, the last_word input must be activated, to indicate that a hash value has to be generated to the core’s output. Along with the last_word, the last_bytes input must indicate how many bytes are valid in the last word, so that the padding unit knows how many bytes to pad.

The core can easily be modified to support programmable Initial Vectors for the Chaining Variables in place of the constants defined in the algorithm’s specification. 

Support

The SHA256 core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The SHA256 core has been verified through extensive simulation and rigorous code coverage measurements. It has also been verified in a prototyping FPGA board platform.

Export Permits

Strong encryption technology is governed internationally by export regulations. Immediate export of the core is permitted to the following countries:

Please contact CAST to discuss delivery to other destinations; approval is subject to the applicable export licenses being granted. Please note that licensees are responsible for complying with the applicable requirements for re-export of electronics containing strong encryption technology.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

• HDL (VHDL or Verilog) RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
• Synthesis script (ASICs) or place and route script (FPGAs)
• Simulation script, vectors and expected results
• Sophisticated self-checking Testbench (Verilog versions use Verilog 2001)
• Software (C++) Bit-Accurate Model
• Comprehensive user documentation, including detailed specifications and a system integration guide
  

On this page: Description | Implementation Results | Applications | Features| Block Diagram | Functional Description | Support | Verification | Export Permits | Deliverables

Download PDF datasheets for more info: ASIC | Altera | Xilinx

 This core developed by the encryption experts at Alma Technologies S.A