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SDIO-HOST SD/SDIO/MMC Memory Card Host Controller Core

On this page: Description | Implementation Results | Features | Applications | Block Diagram | Functional Description | Configurability | Options | Application Example | Support | Verification | Deliverables

The SDIO-HOST core implements an SD/SDIO/MMC memory card host controller compatible with the SDIO Host Specification version 1.00. It supports SD Memory Card 2.00, SDIO Card 2.00, and MultiMediaCard 3.31.

The configurable, multi-slot architecture makes the design suitable for wide range of applications, including low-area designs. The silicon area is below 16k gates for the simple single-slot version without DMA, or as little as 37k gates for the fully-featured 4-slot version. Each slot can be individually controlled through the Standard Register Set, so the internal architecture of the core is transparent for software developers.

The core is developed for reuse in ASIC and FPGA implementations. The design is strictly synchronous with no internal tri-states and a synchronous reset. Therefore scan insertion is straightforward.

See representative implementation results (each in a new pop-up window):

Features

• Compatibility
• SD Memory Card version 2.00 (including SDHC)
• SDIO Card version 2.00
• MMC Card version 3.31
• SDIO Host Specification version 1.00
• General SD interface features
• SD1/SD4 modes of operation
• Suspend/Resume mechanism for SDIO cards
• Read Wait mechanism for SDIO cards
• Multislot operation
• Configurable number of slots (1–4)
• Independent clock/config-uration for each slot
• Independent register set for each slot
• Datapath (including DMA and FIFO) shared between all slots to reduce silicon area
• Standard Register Set
• Compatible with SDIO Host Specification version 1.00
• Independent Interrupt and Wakeup outputs
• Integrated Direct Memory Access (DMA) controller
• Optional, can be removed to reduce silicon area
• Compatible with SDIO Host Specification version 1.00
• Programmable burst length
• Data buffering
• Configurable 32-bit FIFO buffers
• Dual-Buffer mode for optimized throughput
• Dual-Port or Single-Port RAM support
• Low power features
• Master SD card side clock can be switched off
• Each card clock can be switched off independently
• DP RAM can be replaced by SP RAM to reduce power
• Choice of System Interfaces
• Generic 8/16/32-bit master/slave interface
• AMBA AHB™ master/slave interface

Applications

The core makes an excellent memory card controller for handheld consumer electronics such as:

• Digital cameras and camcorders, storing images and video
• Digital audio players and cellular phones, storing media files
• GPS receivers, storing map and waypoint data
• Personal Digital Assistants (PDAs), storing all kinds of data.

It is also suitable for SoC designs interfacing with SDIO Cards or ICs, including:

• 802.11b modems
• Digital Cameras
• Fingerprint recognition cards
• Digital TV tuners
• GPS modules
  

Block Diagram

Functional Description

The core consists of functional blocks as shown in the diagram and briefly described here.

BIU — Bus Interface Unit

Communicates with the host CPU and provides access to the internal register spaces: the Slot Register Set (SRS), Common Register Set (CRS), and proprietary Host Register Set (HRS). The DMA master interface is optional.

CIU — Card Interface Unit

Communicates with SD/SDIO/MMC cards using the SD bus interface. It contains card clock dividers, Command/Response  generation logic (CMD), and SD1/SD4 datapath logic (DAT). Most components are shared between all slots to reduce area; independent components are grouped in a Slot Control Unit (SCU).

FIU  — FIFO Interface Unit

Contains the data buffer control logic for data transactions. In  "dual-buffer" mode, there can be two virtual buffers implemented inside on‑chip RAM, one owned by the BIU side, the other simultaneously accessed by the CIU. The actual memory is implemented outside the core on the chip level, typically either DP‑RAM for high performance (dual-buffer mode) or SP‑RAM for lower power and area.

SYN  — Cross-Clock Domain Synchronization

Provides the logic for reliable cross-clock domain synchronization for all control paths.

RSTC — Reset Controller

Generates reset signals for every internal block of the core, including four reset factors: hardware reset, software reset for all (clears all flip-flops except card detection logic), software reset for CMD (clears command/response logic), and software reset for DAT (clears the datapath logic).

Configurability

Users can control these pre-synthesis options: number of slots (1-4), internal DMA or not, FIFO Buffer size (512B – 2kB), and Data bus width for the Generic Interface.

One of two system bus interfaces are included, either an 8/16/32-bit Generic Interface or a 32-bit AMBA AHBTM Interface. Additional interfaces and further customization are available; contact CAST for details.

Options

FPGA versions are available, and optional extras: an example OS-independent software driver, an evaluation system including board and software, and a reference design for a proprietary development board.

Application Example

This PDA design includes advanced audio-video and communication circuits. Its two-slot SDIO‑HOST core interfaces with external SD Memory cards and communicates with a wireless SDIO modem card.

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The core has been verified through extensive functional and post‑route simulation, and has achieved high Code Coverage. An FPGA prototype was used to check for interoperability with various SD Memory and MMC Cards.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

• Verilog or VHDL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
• Sophisticated, self-checking HDL Test Bench
• Simulation support
• Synthesis script (ASICs) or place and route script (FPGAs)
• Comprehensive documentation

On this page: Description | Implementation Results | Features | Applications | Block Diagram | Functional Description | Configurability | Options | Application Example | Support | Verification | Deliverables

Download PDF datasheet: ASIC | Altera | Xilinx

This core developed by the controller experts at Evatronix SA