PDF datasheets: ASIC Xilinx Related information: News Releases 01/28/02 CAST Adds Ethernet MAC, 64-bit PCI, and CAN Controller to Line of General Purpose IP Cores Articles e-inSITE - CAST Expands IP Core Lineup For more information: contact Sales @ CAST Partnerships: CAST is a member of the PCI-SIG association for PCI standards and interoperability

PCI-T64 64-bit, 66 MHz PCI Target Interface Core

On this page: Description | Implementation Results | Features | Applications | Symbol Diagram | Block Diagram | Functional Description | Support | Verification | Deliverables

The main purpose of the PCI-T64 Interface Core is to isolate the user from having to solve complex problems of PCI interface implementation and let the user focus on the application development.

The PCI-T64 Interface supports a 64-bit address/data bus and operates at up to a 66MHz (PCI clock frequency). It is fully compliant with the PCI Local Bus Specification, Revision 2.3.

The Target supports up to six Base Address Registers with both I/O and Memory space decoding from 16 bytes up to 4GB.

Target supported commands are:

• Configuration Read, Configuration Write
• Memory Read, Memory Write, Memory Read Multiple (MRM), Memory Read Line (MRL),
• I/O Read, I/O Write

See representative implementation results (each in a new pop-up window):

Features

• Flexible VHDL synthesizable core
• PCI specification 2.3 compliant
• 66 MHz performance
• 64-bit data path
• Zero wait states burst mode
• Target functionality
• Single interrupt support
• Type 0 Configuration space
• Support of all Base Address Registers
• Support of backend initiated target retry, disconnect and abort
• Parity generation and parity error detection

Applications

• PCI I/O communication boards
• PCI Data Acquisition Boards
• Embedded system PCI applications

Symbol Diagram

Block Diagram

Functional Description

As shown in the block diagram and explained below, the PCI-T64 includes six major blocks: PCI I/O Interface, Parity Generator, Parity Checker, Configuration Space Registers, Command Register and Address Counter block, Target State Machine.

PCI I/O Interface

The Interface block is responsible for the interface with the PCI Bus. The block implements I/O buffers and I/O registers.

Parity Generator

The parity generator generates parity during read transaction.

Parity Checker

The parity checker checks parity during command phase and write transaction.

Configuration Space Registers

Configuration Space Registers block implements the mandatory 64 bytes of PCI Configuration Space registers. See the chapter PCI Configuration Space for more details.

Target FSM

Target State Machine is a control block of the PCI-T64 interface. The state machine is in charge of handling PCI transactions protocol.

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The core has been verified through extensive simulation and rigorous code coverage measurements.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

• HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
• Sophisticated HDL Testbench
• Simulation script, vectors, expected results, and comparison utility
• Synthesis script (ASICs) or place and route script (FPGAs)
• Comprehensive user documentation, including detailed specifications and a system integration guide

On this page: Description | Implementation Results | Features | Applications | Symbol Diagram | Block Diagram | Functional Description | Support | Verification | Deliverables

Download PDF datasheets for more info: ASIC | Xilinx