NANDFlashCtrl-2Gb
NAND Flash Memory Controller Core
On this page: Description
| Implementation Results | Features
| Applications | Block Diagram
| Functional Description | Application
Example | Support | Verification
| Deliverables
The NANDFlashCtrl-2Gb core implements a flexible
controller for NAND flash memory.
The full-featured core manages the read/write interactions between a
master host system and up to eight NAND Flash memory units. It uses the
standard AMBA™ AHB bus for easy integration with these systems (other
standard interfaces are also available).
Configurable features and internal configuration registers make it easy
to model timing and adapt the core for efficient operation with a variety
memory device types. An internal error code correction calculator (ECC)
helps detect errors, and a power-saving mode makes the NANDFlashCtrl-2Gb
suitable for low-power applications.
The core has been rigorously verified and provides competitive speed
and area results, for example, with a 0.18µ ASIC process it uses
just 5,817 gates and runs at 333 MHz.
The NANDFlashCtrl-2Gb is developed for reuse in ASICs and FPGAs. It
is fully synchronous with positive-edge clocking, has no internal three-state
buses, and uses a synchronous reset, so scan insertion is straightforward.
The included verification package features bus models for the AHB master
and NAND flash devices to help designers verify the functioning of the
core.
See representative implementation results (each
in a new pop-up window):
  
Features
- Supports up to eight memory units:
- Eight chip select and write protection signals
- Allows different memory for each channel
- Configurable features for adaptability to a variety of system and
memory types:
- 3/4 address cycles
- 8/16 IO memory support
- ECC calculation turn on/off
- Address Mode
- Ready/Busy edge detection
- Protected area
- Interrupt request turn on/off
- Read, Write pulse time
- Configurable timing details
- Power Save Mode for low-power applications
- Area Erase/Write Protection
- 256 bytes block error correction code (ECC) calculation
- OK and ERROR responses
- AMBA AHB Slave interface
- 32, 16 bits data bus
- burst transaction support
-
Sophisticated self-checking Testbench (Verilog versions use Verilog 2001)
Applications
The NANDFlashCtrl-2Gb is suitable for integrating NAND flash memory
in both mass storage and embedded memory applications, for example:
- Mass storage — USB flash drives, digital cameras, digital voice
recorders
- Embedded storage — cellular phones, network routers, point
of sale systems.
Block Diagram
Functional Description
The NANDFlashCtrl-2Gb has two main components.
AHB WRAPPER
Responsible for data exchange between the host system's AMBA™ AHB
Master controller and the FLASH CONTROL block in AHB-based systems. (Custom
development of other interfaces is available upon request.)
FLASH CONTROL
Responsible for interfacing with and managing the Flash memory units.
When the external master system requests read or write access to the memory
units, the FLASH CONTROL block generates the appropriate interface transactions.
Access to the memory is always through this block; the master has no direct
connection with the memory.
Application Example
The diagram below shows a typical application for the NANDFlashCtrl-2Gb
in an external mass storage device such as a USB thumb drive.
Support
The core as delivered is warranted against defects for ninety days from
purchase. Thirty days of phone and email technical support are included,
starting with the first interaction. Additional maintenance and support
options are available.
Verification
The core has been verified through extensive simulation and rigorous
code coverage measurements.
Deliverables
The core is available in ASIC (synthesizable HDL) and FPGA (netlist)
forms, and includes everything required for successful implementation:
- HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
- Sophisticated self-checking Testbench (Verilog versions use Verilog 2001) that instantiates the core, bus models of the AHB Master
and a NAND Flash memory device, a clock generator, and processes that
compare actual with expected simulation results
- A collection of tests executed directly by the Testbench
- Simulation script, vectors, expected results, and comparison utility
- Synthesis script (ASICs) or place and route script (FPGAs)
- Comprehensive user documentation, including detailed specifications
and a system integration guide
On this page: Description
| Implementation Results | Features
| Applications | Block Diagram
| Functional Description | Application
Example | Support | Verification
| Deliverables
Download PDF datasheet: ASIC
| Actel | Altera | Xilinx
This core developed by the peripheral controller experts at Evatronix
SA
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