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MAC 10/100 Ethernet Media Access Controller CoreOn this page: Description | Implementation Results | Features | Applications | Symbol Diagram | Block Diagram | Functional Description | Support | Verification | Deliverables Implements a high-speed (10/100 Mbps), half- and full-duplex LAN controller using the Carrier Sense Multiple Access with Collision Detection (CSMA/CD) algorithms defined by IEEE 802.3 for media access control over the Ethernet. For broad compatibility and easy integration, the core works with any
MII-compliant external PHY transceiver. (RMII support is available.) The MAC was developed for reuse in ASIC and FPGA implementations and has been implemented in several commercial products. The design is strictly synchronous with positive-edge clocking, no internal tri-states and with a synchronous reset. See representative implementation results (each in a new pop-up window): Features
ApplicationsThe MAC core can be utilized for a variety of interface applications including network Interface Cards (NICs); routers and switching hubs; and many Systems On Chip (SoC) applications. Symbol Diagram
Block Diagram
Functional DescriptionThe MAC core consists of the following components as shown in the block diagram: TC - Transmit ControllerImplements the 802.3 transmit operation and uses the standard 802.3 MII interface for an external PHY device. Operates synchronously with the clkt clock from the MII interface. BD - Backoff/DeferringImplements the 802.3 half-duplex operation. Operates syn-chronously with the clkt clock from the MII interface. Can be removed for lower gate count if the half-duplex operation is not required. RC - Receive ControllerImplements the 802.3 receive operation using the standard 802.3 MII interface for an external PHY device. Operates synchronously with the clkr clock from the MII interface. TFIFO - Transmit FIFOBuffers data prepared for transmission by the MAC. It provides an interface for the external dual-port RAM working as FIFO memory. The FIFO size can be configured by the generic parameters of the core: TFIFODEPTH defines the total FIFO size; TCDEPTH defines the maximum number of frames that can reside in the transmit FIFO at the moment. Operates synchronously with the clkdma clock from the host Data interface. RFIFO - Receive FIFOBuffers data received by the MAC. It provides an interface for the external dual-port RAM working as FIFO memory. The FIFO size can be configured by the generic parameters of the core: RFIFODEPTH defines the total FIFO size; RCDEPTH defines the maximum number of frames that can reside in the receive FIFO at the moment. Operates synchronously with the clkdma clock from the host Data interface. TLSM - Transmit linked List State MachineImplements the descriptor/buffer architecture of the MAC. It manages the transmit descriptor list, and fetches the data prepared for transmission from the data buffers into the transmit FIFO. Operates synchronously with the clkdma clock from the host Data interface. RLSM - Receive linked List State MachineImplements the descriptor/buffer architecture of the MAC. It manages the receive descriptor list, and moves the data the receive FIFO into the data buffers. Operates synchronously with the clkdma clock from the host Data interface. DMA - Direct Memory Access controllerImplements the host Data interface, servicing both the receive and the transmit channels. Operates synchronously with the clkdma clock from the host Data interface. CSR - Control and Status RegistersUsed by the host to control the MAC operation. Implements the register set, the interrupt controller, and the power management functionality of the MAC, and provides an interface for the host. Operates synchronously with the clkcsr clock from the host CSR interface. RSTC - Reset ControllerResets all components of the MAC. It generates reset signal synchronous to all clock domains in the design from the single external reset line. External componentsThere are three external components required for proper operation of the MAC core:
SupportThe core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available. VerificationThe core has been verified through extensive simulation and rigorous code coverage measurements. DeliverablesThe core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
On this page: Description | Implementation Results | Features | Applications | Symbol Diagram | Block Diagram | Functional Description | Support | Verification | Deliverables Download PDF datasheets for more info: ASIC | Altera | Lattice | Xilinx
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