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MAC-L 10/100 Ethernet MediaAccess Controller Lite Core

On this page: Description | Implementation Results | Features | Applications | Symbol Diagram | Block Diagram | Functional Description | Support | Verification | Deliverables

The MAC-L Ethernet controller is a synthesizable HDL core of a high-speed LAN controller. It implements Carrier Sense Multiple Access with Collision Detection (CSMA/CD) algorithms defined by IEEE 802.3 for media access control over the Ethernet.

There is an interface for external dual port RAMs serving as configurable FIFO memories and there are separate memories for transmit and receive processes. Using the FIFOs additionally isolates the MAC from an external host and provides resolution in case of latency of an external bus.

From the host side the MAC-L uses a generic interface with independent transmit and receive paths. The flexible design allows for using the MAC-L in various applications, especially switching and low gate-count applications.

See representative implementation results (each in a new pop-up window):

Features

• Network interface features
• Supports 10/100Mb/s data transfer rates
• Media Independent Interface (MII)
• Data link layer functionality
• Meets the IEEE 802.3 CSMA/CD standard
• Full or half duplex operation
• Flexible address filtering
• External RAM for storing MAC-L addresses
• Up to 16 physical addresses
• 512 bit hash table for multicast addresses
• External CAM interface
• Transmit/Receive dual port RAM interfaces
• Operates as internal configurable FIFOs
• Programmable threshold levels
• "Store and forward" functionality
• Optional RMII interface

Applications

The MAC-L core can be utilized for a variety of applications including:

• Routers and Switching hubs
• Low gate count applications
• Network Interface Cards (NIC)
• Systems On Chip (SoCs) applications

Symbol Diagram

Block Diagram

Functional Description

The MAC-L core consist of following components:

TC – Transmit Controller

The transmit controller implements the 802.3 transmit operation. From the network side it uses the standard 802.3 MII interface for an external PHY device. The transmit controller operates synchronously with the clkt clock from the MII interface.

BD – Backoff/Deferring

The backoff/deferring controller implements the 802.3 half duplex operation. It operates synchronously with the clkt clock from the MII interface. The backoff/deferring controller can be optionally removed for lower gate-count if the half duplex operation is not required.

RC – Receive Controller

The receive controller implements the 802.3 receive operation. From the network side it uses the standard 802.3 MII interface for an external PHY device. The receive controller operates synchronously with the clkr clock from the MII interface.

TFIFO – Transmit FIFO

The transmit FIFO is used for buffering data prepared for transmission by the MAC-L. It provides an interface for the external dual-port RAM working as FIFO memory. The FIFO size can be configured by the generic parameters of the core. The TFIFODEPTH parameter defines the total FIFO size. The TCDEPTH parameter defines the maximum number of frames that can reside in the transmit FIFO at the same time. The transmit FIFO controller operates synchronously with the clk host side clock.

RFIFO – Receive FIFO

The receive FIFO is used for buffering data received by the MAC-L. It provides an interface for the external dual-port RAM working as FIFO memory. The FIFO size can be configured by the generic parameters of the core. The RFIFODEPTH parameter defines the total FIFO size. The RCDEPTH parameter defines the maximum number of frames that can reside in the receive FIFO at the same time. The receive FIFO controller operates synchronously with the clk host side clock.

External components

For proper operation of the core the following external components are required:

• Transmit Data RAM – Synchronous dual port RAM working as transmit FIFO memory
• Receive Data RAM – Synchronous dual port RAM working as receive FIFO memory
• Address RAM – Synchronous dual port RAM for MAC-L address memory

For more details concerning dual port RAMs refer to the “External dual-port RAM interface” section of the MAC-L user’s guide.

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The core has been verified through extensive simulation and rigorous code coverage measurements.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

• HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
• Sophisticated HDL Testbench including:
• The MAC-L core with memories
• Bus/behavioral models of host and PHY devices
• Clock and reset generators
• Simulation script, vectors, expected results, and comparison utility
• Synthesis script (ASICs) or place and route script (FPGAs)
• Comprehensive user documentation, including detailed specifications and a system integration guide

On this page: Description | Implementation Results | Features | Applications | Symbol Diagram | Block Diagram | Functional Description | Support | Verification | Deliverables

Download PDF datasheets for more info: ASIC | Altera | Lattice

This core developed by the bus interface experts at Evatronix SA