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Ethernet MAC IP Core MAC-L 10/100 Ethernet MediaAccess Controller Lite Core

On this page: Description | Implementation Results | Features | Benefits | Applications | Block Diagram | Functional Description | Options | Configurability | Support | Verification | Example | Deliverables | Related Products

The MAC-L Ethernet controller is a synthesizable HDL core of a high-speed LAN controller. It implements Carrier Sense Multiple Access with Collision Detection (CSMA/CD) algorithms defined by IEEE 802.3 for media access control over the Ethernet.

For broad compatibility and easy integration, the core works with any MII-compliant external PHY transceiver (SMII & RMII support is available.)

The core has an interface for external dual port RAMs serving as configurable FIFO memories with separate memories for transmit and receive processes. Using the FIFOs additionally isolates the MAC from the external host and provides resolution in case of latency of the external bus.

From the host side the MAC-L uses a generic interface with independent transmit and receive paths. The flexible design allows for using the MAC-L in various applications, especially switching and low gate-count applications.

The MAC-L was developed for reuse in ASIC and FPGA implementations. The design is strictly synchronous with positive-edge clocking, no internal tri-states and with a synchronous reset.

See representative implementation results (each in a new pop-up window):

Features

• Network interface features
• Supports 10/100Mb/s data transfer rates
• Media Independent Interface (MII)
• Optional Reduced Media Independent Interface (RMII)
• Optional Serial MII interface instead of standard (SMII)
• Data link layer functionality
• Meets the IEEE 802.3 CSMA/CD standard
• Full or half duplex operation
• Flexible address filtering
• External RAM for storing MAC-L addresses
• Up to 16 physical addresses
• 512 bit hash table for multicast addresses
• External CAM interface
• Transmit/Receive dual port RAM interfaces
• Operates as internal configurable FIFOs
• Programmable threshold levels
• "Store and forward" functionality

Benefits

• Very low gate count per instance makes the IP core an excellent choice for multiport Ethernet devices
• High configurability level makes the controller suitable for a large scope of SoC applications
• Variety of available physical layer interfaces - MII, SMII, RMII gives excellent support for different market solutions

Applications

The MAC-L core can be utilized for a variety of applications including:

• Routers and Switching hubs
• Low gate count applications
• Network Interface Cards (NIC)
• Systems On Chip (SoCs) applications

Block Diagram

Functional Description

The MAC-L core consist of following components:

TC – Transmit Controller

The transmit controller implements the 802.3 transmit operation. From the network side it uses the standard 802.3 MII interface for an external PHY device. The transmit controller operates synchronously with the clkt clock from the MII interface.

BD – Backoff/Deferring

The backoff/deferring controller implements the 802.3 half duplex operation. It operates synchronously with the clkt clock from the MII interface. The backoff/deferring controller can be optionally removed for lower gate-count if the half duplex operation is not required.

RC – Receive Controller

The receive controller implements the 802.3 receive operation. From the network side it uses the standard 802.3 MII interface for an external PHY device. The receive controller operates synchronously with the clkr clock from the MII interface.

TFIFO – Transmit FIFO

The transmit FIFO is used for buffering data prepared for transmission by the MAC-L. It provides an interface for the external dual-port RAM working as FIFO memory. The FIFO size can be configured by the generic parameters of the core. The TFIFODEPTH parameter defines the total FIFO size. The TCDEPTH parameter defines the maximum number of frames that can reside in the transmit FIFO at the same time. The transmit FIFO controller operates synchronously with the clk host side clock.

RFIFO – Receive FIFO

The receive FIFO is used for buffering data received by the MAC-L. It provides an interface for the external dual-port RAM working as FIFO memory. The FIFO size can be configured by the generic parameters of the core. The RFIFODEPTH parameter defines the total FIFO size. The RCDEPTH parameter defines the maximum number of frames that can reside in the receive FIFO at the same time. The receive FIFO controller operates synchronously with the clk host side clock.

External components

For proper operation of the core the following external components are required:

• Transmit Data RAM – Synchronous dual port RAM working as transmit FIFO memory
• Receive Data RAM – Synchronous dual port RAM working as receive FIFO memory
• Address RAM – Synchronous dual port RAM for MAC-L address memory

For more details concerning dual port RAMs refer to the “External dual-port RAM interface” section of the MAC-L user’s guide.

Options

The following optional modules may be ordered according to the user’s application:

• RMII - Reduced MII interface instead of standard MII
• SMII - Serial MII interface instead of standard MII

Configurability

The following parameters allow adjusting the MAC-L to the requirements of the target application or technology.

• data interface bus width – 8 or 16 or 32
• transmit FIFO size – 64B to 64kB
• receive FIFO size – 64B to 64kB

The core is delivered with a standard configuration including BD backoff/deferring module. The backoff/deferring controller can be easily removed for lower gate count if half duplex operation is not required.

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The core functionality was verified in a FPGA prototype working in an Ethernet 10/100 Mbit network.

Example Application

The MAC-L is used to implement 10 and 100 Mbit/s Ethernet networks interface in a system. The example application system consists of the microcontroller (MCU) and the MAC-L module. The host transmits and receives frames through the FIFO memories interfaces (transmit and receive RAMs). The operation mode of the MAC-L is provided via set of configuration pins that can be mapped into microcontroller memory/port(s) or hard-coded to the one desired configuration.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

• HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
• Sophisticated HDL Testbench including external FIFOs, buffers, models of interfaces, the core with memories, bus/behavioral models of host and PHY devices, and clock and reset generators
• Simulation script, vectors, expected results, and comparison utility
• Synthesis script (ASICs) or place and route script (FPGAs)
• Comprehensive user documentation, including detailed specifications and a system integration guide

Related Products

MAC-1G - the most feature-rich controller in the family. Op-erates at 10/100/1000 Mbps speed modes, and contains an integrated descriptor based DMA. Its features include: MII/GMII PHY management, Flow Control, and a full set of Statistical Counters.
MAC-1G-L - optimized for size. It shares the speed of the MAC-1G but with reduced complexity. It communicates with the host using a direct FIFO interface.
MAC - the basic controller in the family. It operates at 10/100 Mbps speed and contains an integrated descriptor based DMA.
R8051XC-MAC-L-HA - an Ethernet controller integrated with the R8051XC Microcontroller core and enriched by a TCP/IP hardware accelerator.
Embedded Ethernet Platform – a complete, configurable embedded Ethernet solution. It demonstrates the functio-nality of the R8051XC MAC L-HA virtual component running in cooperation with the CMX MicroNet™ TCP/IP stack.

On this page: Description | Implementation Results | Features | Benefits | Applications | Block Diagram | Functional Description | Options | Configurability | Support | Verification | Example | Deliverables | Related Products

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