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Ethernet MAC IP Core MAC-L 10/100 Ethernet MediaAccess Controller Lite CoreOn this page: Description | Implementation Results | Features | Benefits | Applications | Block Diagram | Functional Description | Options | Configurability | Support | Verification | Example | Deliverables | Related Products The MAC-L Ethernet controller is a synthesizable HDL core of a high-speed LAN controller. It implements Carrier Sense Multiple Access with Collision Detection (CSMA/CD) algorithms defined by IEEE 802.3 for media access control over the Ethernet. For broad compatibility and easy integration, the core works with any MII-compliant external PHY transceiver (SMII & RMII support is available.) The core has an interface for external dual port RAMs serving as configurable FIFO memories with separate memories for transmit and receive processes. Using the FIFOs additionally isolates the MAC from the external host and provides resolution in case of latency of the external bus. From the host side the MAC-L uses a generic interface with independent transmit and receive paths. The flexible design allows for using the MAC-L in various applications, especially switching and low gate-count applications. The MAC-L was developed for reuse in ASIC and FPGA implementations. The design is strictly synchronous with positive-edge clocking, no internal tri-states and with a synchronous reset. See representative implementation results (each in a new pop-up window): Features
Benefits
ApplicationsThe MAC-L core can be utilized for a variety of applications including:
Block Diagram
Functional DescriptionThe MAC-L core consist of following components: TC – Transmit ControllerThe transmit controller implements the 802.3 transmit operation. From the network side it uses the standard 802.3 MII interface for an external PHY device. The transmit controller operates synchronously with the clkt clock from the MII interface. BD – Backoff/DeferringThe backoff/deferring controller implements the 802.3 half duplex operation. It operates synchronously with the clkt clock from the MII interface. The backoff/deferring controller can be optionally removed for lower gate-count if the half duplex operation is not required. RC – Receive ControllerThe receive controller implements the 802.3 receive operation. From the network side it uses the standard 802.3 MII interface for an external PHY device. The receive controller operates synchronously with the clkr clock from the MII interface. TFIFO – Transmit FIFOThe transmit FIFO is used for buffering data prepared for transmission by the MAC-L. It provides an interface for the external dual-port RAM working as FIFO memory. The FIFO size can be configured by the generic parameters of the core. The TFIFODEPTH parameter defines the total FIFO size. The TCDEPTH parameter defines the maximum number of frames that can reside in the transmit FIFO at the same time. The transmit FIFO controller operates synchronously with the clk host side clock. RFIFO – Receive FIFOThe receive FIFO is used for buffering data received by the MAC-L. It provides an interface for the external dual-port RAM working as FIFO memory. The FIFO size can be configured by the generic parameters of the core. The RFIFODEPTH parameter defines the total FIFO size. The RCDEPTH parameter defines the maximum number of frames that can reside in the receive FIFO at the same time. The receive FIFO controller operates synchronously with the clk host side clock. External componentsFor proper operation of the core the following external components are required:
For more details concerning dual port RAMs refer to the “External dual-port RAM interface” section of the MAC-L user’s guide. OptionsThe following optional modules may be ordered according to the user’s application:
ConfigurabilityThe following parameters allow adjusting the MAC-L to the requirements of the target application or technology.
The core is delivered with a standard configuration including BD backoff/deferring module. The backoff/deferring controller can be easily removed for lower gate count if half duplex operation is not required. SupportThe core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available. VerificationThe core functionality was verified in a FPGA prototype working in an Ethernet 10/100 Mbit network. Example Application
The MAC-L is used to implement 10 and 100 Mbit/s Ethernet networks interface in a system. The example application system consists of the microcontroller (MCU) and the MAC-L module. The host transmits and receives frames through the FIFO memories interfaces (transmit and receive RAMs). The operation mode of the MAC-L is provided via set of configuration pins that can be mapped into microcontroller memory/port(s) or hard-coded to the one desired configuration. DeliverablesThe core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
Related Products MAC-1G - the most feature-rich controller in the family.
Op-erates at 10/100/1000 Mbps speed modes, and contains an integrated
descriptor based DMA. Its features include: MII/GMII PHY management, Flow
Control, and a full set of Statistical Counters.
On this page: Description | Implementation Results | Features | Benefits | Applications | Block Diagram | Functional Description | Options | Configurability | Support | Verification | Example | Deliverables | Related Products Download PDF datasheets for more info: ASIC | Altera | Lattice | Xilnx |
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