Ethernet MAC IP Core MAC-1G 1-Gigabit Ethernet Media Access Controller Core
On this page: Description
| Implementation Results | Features
| Applications | Block Diagram
| Functional Description | Deliverables
The MAC-1G is a flexible, full-featured implementation
of IEEE 802.3-2000 that operates at 10/100/1000 Mbps. It includes a generic
host interface with integrated FIFO logic and DMA controller and can work
with various data path widths and system clock speeds. It provides half-
or full-duplex operation, supports jumbo frames, and includes low-power
features. Its network interface supports any MII/GMII physical layer devices.
Designed for easy reuse, the core uses under 39,000 ASIC gates.
See representative implementation results (each
in a new pop-up window):
Features
- Network interface features
- Supports data transfer rates of 10/100/1000 Mbps
- MII/GMII Media Independent Interface
- PHY management interface*
- Data link layer functionality
- Meets IEEE 802.3 - 2000 specification
- Full- or half-duplex operation
- CSMA/CD procedures for half duplex*
- Flow control for full duplex*
- Jumbo frames support up to 16kB
- Extensive set of MIB statistical counters*
- Flexible address filtering
- Control and status registers
- Configurable 8-, 16-, or 32-bit slave interface
- Single interrupt line
- Interrupt mitigation control mechanism
- DMA controller
- Configurable 8-, 16-, 32-, or 64-bit data bus length
- Configurable address bus length
- Big or little endian data byte ordering
- Scatter/Gather capabilities
- Programmable burst length
- Intelligent arbitration between transmit and receive processes
- Descriptor/buffer architecture
- Descriptor "ring" or "chain" structures
- Single descriptor points to up to two data buffers
- Automatic descriptor list polling
- Low power capabilities
- Independent clocks for data and control paths
- Running/Suspended/Stopped modes of operation
- Clock switching support
- Transmit/Receive dual port RAM interfaces
- Operate as internal configurable FIFOs
- Programmable threshold levels
- Optional RMII & SMII interfaces
* These features can be removed upon request before delivery to achieve
a lower gate count.
Applications
The MAC-1G is ready to serve as a complete network controller that designers
can simply connect to any 8-, 16-, 32-, or 64-bit processor working with
any arbitrary clock frequency. Specific applications include:
- Network Interface Cards (NICs)
- Routers, switching hubs
- Systems On Chip (SOCs)
Block Diagram
Functional Description
The MAC1G core consist of the following blocks:
- TC – Transmit Controller. Implements 802.3 transmit operation.
- RC – Receive Controller. Implements 802.3 receive operation.
- BD – Backoff/Deferring. Implements CSMA/CD algorithms for half
duplex operation.
- FC – Flow Control. Implements flow control (PAUSE functionality)
for full duplex operation.
- SC – Statistical Counters. Implements MIB statistical counters.
- TFIFO – Transmit FIFO. Controls data flow between the MAC and
the Transmit Data RAM.
- RFIFO – Receive FIFO. Controls data flow between the MAC and
the Receive Data RAM.
- TLSM – Transmit Linked List State Machine. Implements descriptor/buffer
architecture.
- TLSM – Receive Linked List State Machine. Implements descriptor/buffer
architecture.
- DMA – Direct Memory Access. Provides the data master interface
for the MAC.
- CSR – Control and Status Registers. Provides access to the internal
registers via slave interface.
- RSTC – Reset Controller. Generates internal reset sig-nals for
all clock domains in the design.
- MIIM – Management Interface. Provides access to in-ternal registers
of the PHY device.
- TPSM – Transmit Process State Machine. Controls the actual status
of the transmit process.
- RPSM – Receive Process State Machine. Controls the actual status
of the receive process.
For proper operation of the core the following external components are
required:
- Transmit Data RAM – Synchronous dual port RAM working as transmit
FIFO memory.
- Receive Data RAM – Synchronous dual port RAM working as receive
FIFO memory.
- Address RAM – Synchronous dual port RAM for MAC physical addresses
/ hash table.
- SC counters RAM – Synchronous RAM for statistical counters.
Deliverables
The core is available in ASIC (synthesizable HDL) and FPGA (netlist)
forms, and includes everything required for successful implementation:
- HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
- Sophisticated HDL Testbench including:
- The MAC1G core
- On chip dual port RAMs
- Bus/behavioral model of host
- Bus/behavioral model of shared RAM
- Bus/behavioral model of PHY device
- Clock generators
- Reset generator
- Processes that compare your simulation results with the expected
results
- Simulation script, vectors, expected results, and comparison utility
- Synthesis script (ASICs) or place and route script (FPGAs)
- Comprehensive user documentation, including detailed specifications
and a system integration guide
On this page: Description
| Implementation Results | Features
| Applications | Block Diagram
| Functional Description | Deliverables
Download PDF datasheets for more info: ASIC
| Altera | Xilinx
|
