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MAC-1G-PCS Gigabit Ethernet MAC Controller Physical Coding Sublayer

On this page: Description | Implementation Results | Features | Block Diagram | Functional Description | Example Application | Deliverables

The MAC-1G PCS is an IP core of a 1 Gigabit Physical Coding Sublayer (PCS) that meets all IEEE 802.3-2002 Standard requirements. The MAC-1G PCS provides both PCS interfaces, GMII and PMA. It also features the Management Interface (MGM) for communication with the Station Management (STA).

The MAC-1G PCS has been developed for reuse in ASIC and FPGA implementations. The design is strictly synchronous with positive-edge clocking, no internal tri-states and a synchronous reset; therefore, scan insertion is straightforward.

See representative implementation results (each in a new pop-up window):

Features

• IEEE 802.3-2002 Standard compliance
• Configurable and monitorable through the Management Interface
• 1000BASE-X Auto-Negotiation process support for information data exchange with a link partner
  8B-10B Data Encoder/Decoder
• Synchronization Module
• MAC frames encapsulation/de-encapsulation
• Data transmitting/receiving
• Carrier-extension transmitting/receiving
• Idle ordered sets for transmitting/receiving
• Full and half duplex mode support
• Standard Register Set
• PHY loopback mode support with MGM write control register command

Benefits

• Possibility for FPGA implementation with 8B-10B Data Encoder/Decoder located in built-in memory blocks
• Perfect for integrating an Ethernet MAC controller with an optical transceiver through Physical Medium Attachment (PMA) sublayer

Block Diagram

Functional Description

The MAC-1G PCS IP core is partitioned into modules as shown in the figure above and described below.

Transmit Module

This provides Ethernet MAC data packets encapsulation and de-encapsulation and sends them to the PMA, as well as generates code-groups based upon the signals delivered from GMII. GMII data octets are converted into the ordered sets according to the state diagram of IEEE 802.3-2002. The module provides continuous fill pattern during inter-packet gaps to establish and maintain clock synchronization. It also supports the Auto-Negotiation process.

Receive Module

This component recognizes data and special code-groups received from the PMA, as well as detects and interprets ordered-sets sent by the link partner according to the state diagram of IEEE 802.3-2002. It also generates appropriate signals on the GMII Interface.

8B/10B Encoder

The module encodes 8-bit data and special groups into 10-bit code-groups depending on the current running disparity. It counts running disparity based upon last encoded code-group and ensures DC balanced bit-stream and high transition density to facilitate clock recovery.

Carrier Sense

This provides detection of a carrier in a received data. This is used for detection of valid data transmission and crs and col signals generation.

Auto – Negotiation Module

This component sets the working mode for the Transmit Module by informing transmit logic to either transmit normal idles interspersed with data packets from Ethernet MAC or to reconfigure the link by the auto-negotiation (AN) process. It is also responsible for setting the status registers and ability advertisement of link partner registers for use by the Station Management (STA), as well as for reading/writing configuration registers of the Management Registers unit. The module supports management registers from 0 to 6 and register number 15 (basic set plus some from extended set).

Synchronization Module

This accepts code groups received from the PMA and conveys them to the Receive Module. It checks if received code groups are valid and informs AN module about lost or obtained synchronization. This information is further used to establish appropriate work mode.

8B/10B Decoder

The Decoder provides decoding of 10-bit data and special groups into 8-bit code-groups and supports invalid or faulty code groups detection.

Management Registers Module

This provides the Base Register Set, which is a set of six dedicated management registers, as well as the MGM Interface for communicating with Station Management (STA). The module implements a mechanism to read/write status and configuration registers. Management Registers also communicate with the Auto-Negotiation Module to ensure data and ordered sets exchange between the PCS and the Station Management.

Example Application

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

• HDL RTL source code (soft core) or a post-synthesis EDIF netlist (firm core)
• Sophisticated self-checking HDL Testbench
• Simulation scripts, vectors, expected results, and comparison utility
• Synthesis (soft) or place and route (firm) script
• Comprehensive user documentation, including detailed specifications and a system integration guide

On this page: Description | Implementation Results | Features | Block Diagram | Functional Description | Example Application | Deliverables

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This core developed by the networking experts at Evatronix SA