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JPEG2K-E JPEG 2000 Encoder CoreOn this page: Description | Applications | Features | Block Diagram | Functional Description | Support | Verification | Deliverables | Examples The JPEG2K-E core is a complete high performance JPEG2000 - ISO/IEC 15444-1 image compression solution targeted for video and high bandwidth image compression applications . Implementing in custom hardware tier-1 and tier-2 encoding (including rate control), the core once programmed can receive pixel data and output fully compliant stream at the desired compression ratio. Furthermore, being able to support frame/tile sizes up to 4096 x 4096 pixels, and providing processing rates upto 150 MSamples/sec, JPEG2K-E eliminates the need for parallel processing even for the most demanding application such as HDTV. The JPEG2K-E is a reliable and easy-to-integrate core as it is carefully designed, and rigorously verified. The architecture can be fine-tuned based on the application specific needs. Ease of integration is served by a complete verification environment, and additional aids for system on chip simulation, such as a software bit-accurate model. See representative implementation results (each in a new pop-up window):
ApplicationsThe JPEG2K-E can be utilized in a variety of multimedia applications including:
Features
Block Diagram
Functional DescriptionThe JPEG2K-E operates either on an entire image or on a rectangular section of an image called a tile. The maximum supported image/tile size depends on the size of the external memory, while provided enough external memory the core can support up to 4096x4096 images. The default configuration of the core embeds an SDRAM controller. However, JPEG2K-E configurations working with DDR/DDR2, or SRAM or QDR-SRAM can be made available on demand. Synthesis and run-time parameters allow customization of the core for compression performance, area speed and memory trade-offs. In terms of internal operation, the input pixels are first level-shifted and then transformed using either the reversible 5/3 or the irreversible 9/7 two-dimensional discrete wavelet transform; the transformed coefficients are stored in the external memory. After an entire tile has been transformed, the transformed coefficients are quantized; the quantized coefficients are fed to the Entropy Coding Engines in a code-block per code-block basis. The coded-segments along with the code-block attributes (truncation lengths and distortion metrics) produced by the Entropy Coding Engines are fed to the Rate Control Engine. If enabled, the Rate Control Engine implements a proprietary PCRD algorithm that outputs code-stream at the required compression ratio with the minimum possible quality loss. Finally the Headers-Syntax Unit forms global, tile and packet headers, and outputs a compliant stream or file. SupportThe core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available. VerificationThe core has been verified through extensive simulation and rigorous code coverage measurements. It has also been embedded in several products, and is proven in both ASIC and FPGA technologies. DeliverablesThe core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
Image Compression ExamplesThe following samples depict the images and whole-photo file sizes resulting from JPEG 2000 (JP2) and JPEG (JPG) encoding at 20:1 and 75:1 compression levels, and JPEG 2000 Lossless (JP2 LL) encoding.
On this page: Description | Applications | Features | Block Diagram | Functional Description | Support | Verification | Deliverables | Examples Download PDF datasheets for more info: ASIC | Altera | Xilinx
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