PDF datasheets: See Options Options for this core: ahb apb apb-a Related information: Articles WHATIS.COM - definition EDUCYPEDIA - I2C and I2S links to spec, FAQs, etc. For more information: contact Sales @ CAST

I2S Inter-IC Sound Bus Core

The I2S core integrates eight channels of Inter-IC Sound compatible serial buses. It is typically used to integrate up to eight audio transmission channels into an application-specific integrated circuit (ASIC) or a system-on-a-chip (SoC) design.

I2S is a well known stereo audio transmission standard, widely used when interconnection is needed between system elements as, Analog to Digital AD and Digital to Analog DA converters.

I2S-AHB option

By using the I2S-AHB module in the SoC design, a designer can easily integrate the core used for multi-channel audio transmission with the master system based on a standard AHB bus for further data processing.

Data collected by the I2S-AHB core is stored in the internal core’s FIFO. This use of internal FIFO allows the system to process the relatively slow audio stream in the interrupt triggered subroutines.

The collected data can then be easily and quickly accessed by the master system on the AHB bus by any AHB bus master that is able to perform single or burst accesses on the AMBA bus.

I2S-APB option

By using the I2S-APB module in a SoC design, a designer can easily integrate the core used for multi-channel audio transmission with the master system based on a standard AMBA APB bus for further data processing.

The data collected by the I2S-APB core is stored in the core’s internal FIFO. This use of an internal FIFO allows the system to process the relatively slow audio stream in the interrupt-triggered subroutines.

The collected data can then be easily and quickly accessed by the master system by the AMBA APB bus by any APB bus master.

Reference designs have been evaluated in a variety of technologies. Click on a technology button to see results for each core version using that technology. All results are optimized for speed, without the DMA Controller or debugging options.

Download PDF datasheets for more info: hdl-ahb | hdl-apb | hdl-apb-a

This core developed by the bus interface experts at Evatronix SA