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I2CS Philips Serial Bus Interface Slave Core

On this page: Description | Implementation Results | Features | Applications | Symbol Diagram | Block Diagram | Support | Verification | Deliverables

The I2CS Bus Controller logic provides a serial interface that meets the Philips I2C bus specification and supports all slave transfer modes to and from the I2C bus. The I2CS logic handles bytes transfer autonomously. It also keeps track of serial transfers, and a status register (i2cssta) reflects the status of I2CS Bus Controller and the I2C bus.

Developed for easy reuse with ASICs or FPGAs, the core requires under 900 ASIC gates.

See representative implementation results (each in a new pop-up window):

Features

• Uses two wires to transfer information between devices
• Serial Clock Line SCL (SCL)
• Serial Data Line (SDA).
• Performs serial transmission with data transfers up to 100 Kbps in standard mode and up to 400 Kbps in fast-mode
• Slave Receiver Mode - Serial data and the serial clock are received through SDA and SCL
• Slave Transmitter Mode - Serial data is transmitted via SDA while the serial clock is input through SCL
• Bi-directional data transfer
• Own address and General Call address detection
• 7 bit addressing format
• Fixed data width of 8 bits
• Data transfer in multiples of bytes
• One-byte write and read buffer
• Strictly synchronous design with positive-edge clocking, no internal tri-states and a synchronous reset; therefore scan insertion is straightforward

Applications

The I2CS can be utilized for a variety of serial interface applications.

Symbol Diagram

Block Diagram

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The I2CS core’s functionality was verified by means of a proprietary hardware modeler. The same stimulus was applied to a hardware model that contained the original Philips 80C552 chip, and the results compared with the core’s simulation outputs.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

• HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
• Sophisticated HDL Testbench including external FIFOs, buffers, models of interfaces, and the core
• Simulation script, vectors, expected results, and comparison utility
• Synthesis script (ASICs) or place and route script (FPGAs)
• Comprehensive user documentation, including detailed specifications and a system integration guide

Patent Notice: Supply of this core does not convey nor imply a right under the I2C patent rights of Royal Philips Electronics N.V. to make use or sell any product employing these patent rights. An I2C patent license from Royal Philips Electronics N.V. is required for any use of such patent rights, including the implementation of this core in an Integrated Circuit or any other device.

On this page: Description | Implementation Results | Features | Applications | Symbol Diagram | Block Diagram | Support | Verification | Deliverables

Download PDF datasheets for more info: ASIC | Altera

This core developed by the bus interface experts at Evatronix SA