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I2C Philips Serial Bus Interface Core

On this page: Description | Implementation Results | Features | Applications | Symbol Diagram | Block Diagram | Functional Description | Support | Verification | Deliverables

I2C Bus Controller logic provides a serial interface that meets the Philips I2C bus specification and supports all transfer modes from and to the I2C bus.

The I2C logic handles bytes transfer autonomously. It also keeps track of serial transfers, and a status register (i2csta) reflects the status of I2C Bus Controller and the I2C bus.

The I2C is a microcode-free design developed for reuse in ASIC and FPGA implementations. The design is strictly synchronous with positive-edge clocking, no internal tri-states and a synchronous reset; therefore scan insertion is straightforward.

See representative implementation results (each in a new pop-up window):

Features

The I2C bus uses two wires to transfer information between devices connected to the bus: SCL (serial clock line) and SDA (serial data line).

• Master Transmitter Mode — Serial data output through SDA while SCL outputs the serial clock.
• Master Receiver Mode — Serial data is received via SDA while SCL outputs the serial clock.
• Slave Receiver Mode — Serial data and the serial clock are received through SDA and SCL.
• Slave Transmitter Mode — Serial data is transmitted via SDA while the serial clock is input through SCL.
• Data transfers up to 100 Kbps in standard mode and up to 400 Kbps in fast-mode.
• Bi-directional data transfer.
• Own address and General Call address detection.
• 7-bit addressing format.
• Fixed data width of 8 bits.
• Data transfer in multiples of bytes.
• One-byte write and read buffer.
  

Applications

The I2C can be utilized for a variety of bus applications including:

• Embedded microcontroller systems
• Communication systems

Symbol Diagram

Block Diagram

Functional Description

The I2C core is partitioned into modules as shown in figure 1 and described below.

Arbitration and synchronization logic

In the master mode, the arbitration logic checks that every transmitted logic 1 actually appears as a logic 1 on the I2C bus. If another device on the bus overrules a logic 1 and pulls the SDA line low, arbitration is lost and the I2C immediately changes from master transmitter to slave receiver. The synchronization logic will synchronize the serial clock generator with the clock pulses on the SCL line from another device.

Serial clock generator

This programmable clock pulse generator provides the SCL clock pulses when the I2C is in the master mode. The clock generator is switched off when the I2C is in a slave mode.

Control logic

The control logic generates the control signals for serial byte handling.

Input filter

Input signals are synchronized with the internal clock (clk), and spikes shorter than three oscillator periods are filtered out.

Address comparator

The comparator compares the received 7-bit slave address with its own slave address. It also compares the first received 8-bit byte with the general call address (00H). If equality is found, the appropriate status bits are set and an interrupt is requested.

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The I2C core’s functionality was verified by means of a proprietary hardware modeler. The same stimulus was applied to a hardware model that contained the original Philips 80C552 chip, and the results compared with the core’s simulation outputs.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

• HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
• Testbench
• Simulation script, vectors, expected results, and comparison utility
• Synthesis script (ASICs) or place and route script (FPGAs)
• Comprehensive user documentation, including detailed specifications and a system integration guide

On this page: Description | Implementation Results | Features | Applications | Symbol Diagram | Block Diagram | Functional Description | Support | Verification | Deliverables

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This core developed by the bus interface experts at Evatronix SA