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H264-E HD H.264/AVC Video Encoder CoreOn this page: Description | Applications | Features | Block Diagram | Functional Description | Support | Deliverables The Η264-Ε core implements a video encoder in hardware that uses the Baseline profile H.264 Advanced Video Coding (AVC) standard (level 4.1), also known as MPEG-4 Part 10. It receives video frames in a standard format, outputs the H.264 encoded bit-stream, and saves decoded reference frames to an external memory. It can process up to 1080p HDTV video (1920 x1080 pixels, progressive). The efficient core requires minimal host intervention: it only needs to be programmed once with the encoding options, and it can then encode an arbitrary number of video frames. The core’s simple and flexible external memory interface makes it independent of memory type—supporting SRAM, SDRAM, or DDRAM—and tolerant to the large delays and latencies typically present on a shared bus architecture. The core is designed for reuse and reliability, and has been rigorously verified. Developed for easy integration, it includes a complete verification environment plus additional aids for system-on-chip simulation such as a software bit-accurate model (BAM). ApplicationsThe H264-E core is suitable for a wide range of High-Definition (HD) and Standard Definition (SD) video rates and applications, including:
FeaturesH264 Encoding
Integration Support
Block Diagram
Functional DescriptionThe H264-E core is a hardware implementation of the H.264 baseline video compression algorithm, designed to process up to 1080p HDTV video. It consists of a number of functional blocks, as shown in the diagram and described here. For each block of pixels, the Intra Prediction unit generates a suitable prediction. In the case of P-frames, the Motion Estimation Unit also generates a prediction, operating with sub-pixel accuracy. The prediction cost of each unit is estimated using Lagrange multipliers, and the best is selected for encoding. The residual information is calculated from the difference between the current block and the prediction. It is then transformed and quantized to be encoded by the Entropy Encoding unit. The transformed, quantized residual is also used to reconstruct a reference frame, which will be used during the encoding of future P-frames. This is achieved by inverse quantization and transformation of the residual, which is then added back to the prediction. Finally, the reconstructed frame is filtered before being stored back in the external memory. The core includes a Deblocking Filter and can perform macroblock skipping. Both of these features are important for low data rate applications. SupportThe core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available. DeliverablesThe core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
On this page: Description | Applications | Features | Block Diagram | Functional Description | Support | Deliverables Download PDF datasheets for more info: ASIC
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