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H16550S UART with Synchronous CPU Interface Core

On this page: Description | Implementation Results | Features | Applications | Symbol | Block Diagram | Functional Description | Support | Verification | Deliverables

The H16550S is a standard UART providing 100% software compatibility with the popular Texas Instruments 16550 device. It performs serial-to-parallel conversion on data originating from modems or other serial devices, and performs parallel-to-serial conversion on data from a CPU to these devices.

The H16550S can be run in either 16450- compatible character mode or in 16550- compatible FIFO mode, where an internal FIFO relieves the CPU of excessive software overhead.

Developed for easy reuse in FPGA or ASIC applications, the H16550S is available optimized for several technologies with competitive utilization and performance characteristics.

See representative implementation results (each in a new pop-up window):

Features

• Capable of running all existing 16450 and 16550a software
• Fully Synchronous design. All inputs and outputs are based on rising edge of clock
• In FIFO mode, the transmitter and receiver are each buffered with 16 byte FIFOs to reduce the number of interrupts presented to the CPU
• Adds or deletes standard asynchronous communication bits (start, stop and parity) to or from the serial data
• Independently controlled transmit, receive, line status and data set interrupts
• Programmable baud generator divides any input clock by 1 to (216 - 1) and generates the 16 x clock
• Modem control functions (CTSn, RTSn, DSRn, DTRn, RIn, and DCDn)
• Fully programmable serial interface characteristics:
• 5, 6, 7, or 8 bit characters
• Even, odd, or no-parity bit generation and detection
• 1, 1½, or 2 stop bit generation
• Baud generation
• False start bit detection
• Complete status register
• Internal diagnostic capabilities: loopback controls for communications link fault isolation
• Full prioritized interrupt system controls

Applications

The H16550S core can be utilized for many communication applications including:

• Serial or modem computer interface
• Serial interface within modems and other devices

Symbol Diagram

Block Diagram

Functional Description

As shown in the block diagram and explained below, the H16550S includes six major blocks: Interface, Registers, RXBlock, Interrupt Control, Baud Rate Generator, and TXBlock. All inputs and outputs for the H16550S are fully synchronous to the rising edge of the CLK input.

Interface

The Interface block is responsible for handling the communications with the processor (or parallel) side of the system. All writing and reading of internal registers is accomplished through this block.

Registers

The Registers block holds all of the device’s internal registers. See the Register Description table for details on existing registers and their addresses. Some information comes from the other blocks, but this is all gathered together in the Registers block and made available to all blocks.

RXBlock

This is the receiver block. It handles the receiving of the incoming serial word. It is programmable to recognize data widths such as 5, 6, 7 or 8 bits, various parity settings such as even, odd or no parity and different stop bits of 1, 1½ and 2 bits. It checks for errors in the input data stream such as overrun errors, frame errors, parity errors and break errors. If the incoming word has no problems it is placed either in the Receiver Holding register or in the Receiver FIFO depending on the mode programmed.

Interrupt Control

The Interrupt Control block sends an interrupt signal back to the processor depending on the state of the FIFO and its received and transmitted data. There are various levels of interrupt which can be read from the Interrupt Identification register, which gives the level of interrupt. Interrupts are sent in the condition of empty transmission or receiving buffers (or FIFOs), an error in the receiving of a character, or other conditions requiring the attention of the processor.

Baud Rate Generator

This block takes the input clock, CLK, and divides it by a programmed value (from 1 to 216 – 1). This divided clock is then divided by 16 to create the transmission clock called the Baudout clock.

TXBlock

The Transmit block handles the transmission of data written to the Transmission Holding register (or transmit FIFO). It adds required start, parity and stop bits to the data being transmitted so that the receiving device can do the proper error handling and receiving.

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The core has been verified through extensive simulation and rigorous code coverage measurements.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

• HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
• Wrapper for pin compatible replacement
• Sophisticated HDL Testbench (self-checking)
• Simulation script, vectors, expected results, and comparison utility
• Synthesis script (ASICs) or place and route script (FPGAs)
• Comprehensive user documentation, including detailed specifications and a system integration guide

On this page: Description | Implementation Results | Features | Applications | Symbol | Block Diagram | Functional Description | Support | Verification | Deliverables

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