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EPP_Slave Extended Parallel Port Interface Slave Core

On this page: Description | Implementation Results | Features | Applications | Symbol Diagram | Functional Description | Support | Verification | Deliverables

The Enhanced Parallel Port (EPP) interface is a standard protocol that permits bi-directional data transfer between a personal computer and a peripheral device. Data transfer rates may vary between 500 kbytes/s and 2000 kbytes/s, depending on the EPP master implementation in the host PC. The EPP slave is ideal for interfacing to a PC through the widely used Parallel Port, easily and with low cost, without having to develop sophisticated software drivers. It is suited for peripherals that require relatively high data transfer rates and bi-directional data transfer.

The core implements EPP version 1.9, which is compatible with both EPP 1.9 and 1.7 hosts. It was carefully designed to provide reliable communication, and a prototype peripheral using the core was developed and exercised during the testing procedures.

The EPP_Slave core is a fully synchronous design. The core is available in both VHDL and Verilog and the code is technology independent.

See representative implementation results (each in a new pop-up window):

Features

• EPP 1.9 compliant, based on IEEE 1284
• High speed (0.5 – 2Mbytes/s), half duplex, asynchronous parallel data transfer
• Slave mode
• Interlocked handshakes on both EPP side and peripheral side
• Fully synchronous design, one clock domain, no latches
• Technology independent VHDL or Verilog source code

Applications

The EPP_SLAVE can be utilized for a variety of applications including:

• Low cost bidirectional communication with a PC
• Data acquisition systems
• In circuit emulators
• EPROM programmers
• Instruments
• Experimental platforms
  

Symbol Diagram

Functional Description

From the peripheral side, a generic microprocessor bus interface is implemented, using interlocking handshakes. This means that there are acknowledge signals that depend on each other. For example, in case of an EPP read transaction, the EPP slave will wait for the peripheral to assert the ready flag before sending a re pulse to it. The EPP core will wait until the peripheral sends back an acknowledge signal (data_valid) to indicate that data fed to the core’s input are valid. Then the core passes the data to the EPP host and asserts epp_nwait, which is the acknowledge signal used by the EPP to end the transaction. By using interlocked handshakes, the peripheral can extend the EPP transaction for a short period of time, enough to be able to respond.

The peripheral sees the host PC through the parallel port as an external microprocessor. The core provides to the peripheral 8-bit input and output data buses, an 8-bit address bus, read / write strobes and handshake signals. The PC always plays the role of the master and initiates read or write transactions.

One global clock domain is used in the fully-synchronous core. All flip-flops are triggered with the positive edge of the clock, and no latches are used. Tristate enable signals are provided for use with tristate buffers in the top level where needed to combine input and output buses to a single bi-directional bus.

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The EPP_Slave core was implemented on a general purpose prototyping platform and tested with several host PCs.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

• HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
• Wrapper for pin compatible replacement
• Sample software accessing the EPP port under win95/98/Me or win NT/2000/XP
• Sophisticated self-checking Testbench (Verilog versions use Verilog 2001)
• Simulation script, vectors, expected results, and comparison utility
• Synthesis script (ASICs) or place and route script (FPGAs)
• Comprehensive user documentation, including detailed specifications and a system integration guide
• Design support

On this page: Description | Implementation Results | Features | Applications | Symbol Diagram | Functional Description | Support | Verification | Deliverables

Download PDF datasheets for more info: ASIC | Altera | Xilinx

 This core developed by the interface experts at Alma Technologies S.A