CUSB2 High Speed USB Device Controller Core
On this page: Description
| Implementation Results | Features
| Applications | Block Diagram | Deliverables
The CUSB2 core implements a complete high/full-speed
(480/12 Mbps) peripheral controller that interfaces to a UTMI USB port
transceiver on one side and to a system’s microprocessor on the
other. It is user-configurable for up to 15 IN and OUT endpoints, and
includes power management and remote wake-up functions.
Options include an integrated configuration/enumeration FSM, support
for the Philips ISP1501 transceiver, and a UTMI Low Pin Interface (ULPI).
Designed for easy reuse in ASIC and FPGA implementations, the microcode-free
design is strictly synchronous with positive-edge clocking, no internal
tri-states and a synchronous reset; therefore scan insertion is straightforward.
See representative implementation results (each
in a new pop-up window):
Features
- Full compliance with the USB 2.0 specification
- Control endpoint 0 — fixed 64 Bytes size
- Configurable for up to 15 IN and 15 OUT endpoints
- Configurable/programmable number and size of endpoints
- Configurable/programmable single, double, triple or quad buffering
- Programmable type of endpoints
- UTMI Transceiver Macrocell Interface. Optional UTMI Low Pin Interface
(ULPI).
- Configurable 8-, 16-, or 32-bit microprocessor interface
- Easy integration with a wide range microprocessors and bus architectures
- Interrupt request signals for application microprocessor
- Interrupt vector for autovectored interrupts
- Direct access to the endpoints buffers via configurable 8-, 16-,
or 32-bit Slave FIFO interface
- Ready for external DMA module
- Synchronous RAM interface for FIFOs
- Suspend and resume power management functions
- Remote Wake-Up function
- Optional configuration/Enumeration FSM can be added before delivery
- Support for USB standard requests (described in Chapter 9 of
the USB Specification)
- Interface for asynchronous ROM with the USB function descriptors
- Optional support for Philips ISP1501 USB2.0 Transceiver can be added
before delivery
- Sophisticated self-checking Testbench (Verilog versions use Verilog 2001)
Applications
- Embedded microcontroller systems
- Communication systems
Block Diagram
Deliverables
- VHDL or Verilog HDL source code
- Post-synthesis EDIF netlist (netlist license)
- Sophisticated self-checking Testbench (Verilog versions use Verilog 2001)
- Vectors for testing the core
- Place & route scripts (netlist license)
- Simulation & synthesis scripts
- Documentation
On this page: Description
| Implementation Results | Features
| Applications | Block Diagram | Deliverables
Download PDF datasheets for more info: ASIC
| Altera | Lattice
| Xilinx
This core developed by the bus interface experts at Evatronix
SA
|
