Request more info on this core PDF datasheets: ASIC Actel Altera Lattice Xilinx Options for this core: CUSB software stack Related information: Validated for Precision™ FPGA Synthesis News Releases 06/18/01 CAST Releases USB 1.1 IP Core Resources For an excellent USB overview, see Which version of USB is right for your application?, by Dan Harmon, at Planet Analog

USB IP Core CUSB Universal Serial Bus Device Controller Core

On this page: Description | Implementation Results | Features | Applications | Software | Block Diagram | Functional Description | Deliverables

The CUSB is a USB Device Controller that provides USB full speed function interface that meets the 1.1 revision of the USB specification. The CUSB logic handles bytes transfer autonomously and bridges USB interface to a simple read/write parallel interface. The CUSB can be customized and optimized for a specific application. It contains a set of Special Function Registers that is similar to the Cypress EZ-USB FX chip.

The microcode-free design was developed for reuse in ASICs and FPGAs. The design is strictly synchronous with positive-edge clocking, no internal tri-states and a synchronous reset. Scan insertion is straightforward.

See representative implementation results (each in a new pop-up window):

Features

• Serial Interface Engine
• Support full speed devices
• Extraction clock and data signals in internal DPLL
• NRZI decoding/encoding
• Bit stuffing/stripping
• CRC checking/generation
• Interface for an external transceiver
• Up to 31 configurable endpoints
• Support control transfers by endpoint 0
• Support bulk, interrupt and isochronous transfers
• Double buffering for isochronous endpoints
• Programmable double buffering for bulk and interrupt endpoints
• Automatic data retry mechanism
• Data toggle synchronization mechanism
• Suspend and resume power management functions
• Remote Wake-Up function
• Endpoint buffers RAM interface
• Up to 2 x 1024 Bytes FIFO size for isochronous endpoints
• Up to 64 Bytes buffer size for each bulk, interrupt and control endpoints
• Microcontroller interface
• Asynchronous address and data bus interfaces, and read and write control signals. (Internally synchronized within the CUSB core)
• Interrupt request signals for application microcontroller
• Interrupt vector for autovector interrupts
• Optional Features
  • DMA Controller
  • Software Stack

Applications

• Embedded microcontroller systems
• Communication systems

Software

A complete software stack with the most popular device classes is available. It has been designed for portability in a variety of embedded applications. It includes an intuitive Application Programming Interface (API) for application development.

Block Diagram

Functional Description

The CUSB core is partitioned into modules as shown in the block diagram and described below:

Serial Interface Engine - SUBSIE

The CUSBSIE logic contains a Digital Phase Locked Loop (DPLL) that uses 4 times over-sampling of the USB data stream for clock extraction. It is able to track jitter and frequency drift as specified by the USB Specification Rev. 1.1. The CUSBSIE performs serial data decoding/encoding, bit stuffing/stripping and CRC checking/generation. Received/transmitted data are grouped in bytes and transferred to/from the CUSBPIE.

Parallel Interface Engine - CUSBPIE

The CUSBPIE contains a set of Special Function Registers (SFR) that are provided to control the CUSB behavior, the logic that handles all USB transfers and interfaces for end-points buffers and for the microcontroller.
The CUSBPIE supports these types of USB data transfers:

• Control transfer – transfer request commands from host to device
• Interrupt transfer – data transfer from an interrupt driven device to host
• Bulk transfer – transfer for a large amount of data
• Isochronous transfer – for application requiring constant data transfer rate

SFRS

The SFRS contains set of Special Function Registers which are used to control the CUSB operation.

Implementation Results

CUSB reference designs have been evaluated in a variety of technologies.

FPGA results:   Altera | Lattice | Xilinx

Deliverables

• VHDL or Verilog HDL source code
• Post-synthesis EDIF netlist (netlist license)
• Testbench (self-checking)
• Vectors for testing the core
• Place & route scripts (netlist license)
• Simulation & synthesis scripts
• Documentation

On this page: Description | Implementation Results | Features | Applications | Software | Block Diagram | Functional Description | Deliverables

Download PDF datasheets for more info: ASIC | Actel | Altera | Lattice | Xilinx