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PCIe Endpoint IP Core CPXP-EP PCI Express Endpoint Controller Core with SoC Bridge Extensions for AHB, AXI and Wishbone CoreOn this page: Description | Implementation Results | Features | Applications | Block Diagram | Functional Description | Support | Verification | Deliverables Implements a PCI Express endpoint controller that is compliant with PCI Express Base specification 1.1, including the Transaction, Data Link, and Physical protocol layers. It is available to act as a bridge to standard buses including AMBA™ AHB, AMBA™ AXI and Wishbone. The scalable and flexible core has a modular architecture and a high-performance, low-latency design. It supports multiple device link widths to better match the bandwidth needs of specific applications—x1 (single lane) and x4 (four lane)—and offers bi-directional data rates from 250MB/s (x1) to 1GB/s (x4). It supports most advanced PCI Express capabilities, including message signaled interrupts, multiple virtual channels, advanced error reporting, end-to-end cyclic redundancy check, and power management features. Multi-lane versions of the core support lane reversal and polarity inversion. The core has an Application Interface (AIF) layer that makes integration significantly easier than the transaction layer packet (TLP) interface typically provided. This AIF includes a DMA controller and provides a higher-level connection between the core logic and the user’s application. Interfaces to standard system buses such as Wishbone or AMBA™ AHB are available. The external connection interface from the core conforms to the Intel® PIPE specification, ensuring compatibility with any 16-bit PIPE-compliant physical layer (PHY). The core has been successfully used with PHYs from multiple vendors. The synchronous, latch-free core design was rigorously verified for compliance with the PCI Express specification, and has passed PCI-SIG certification. The core has been tested for interoperability with multiple motherboards using chipsets from various vendors, and is in use by multiple customers. See representative implementation results (each in a new pop-up window):
Features
Integration
Certification
ApplicationsPCI Express is rapidly being adopted for a variety of interconnection applications, including:
Block Diagram
Functional DescriptionThe core is divided into four modules responsible for the Configuration Space, Transaction Layer, Data Link Layer, and Physical Layer MAC. Configuration SpaceProvides a Configuration space register file type 0. In addition to the mandatory functions, numerous extended capabilities are also supported. Transaction Layer moduleResponsible for the assembly and disassembly of transaction layer packets. The transaction layer supports four address spaces: Configuration space, Memory space, I/O space and Message Space. Power management services are supported. Data Link Layer moduleResponsible for link management, data protection and integrity checking, retry and power management services. Physical Layer MAC moduleImplements the logical sub-block of the physical layer. The module is responsible for link training and status monitoring, link width negotiation, lane order negotiation, lane polarity reversal control and power management implementation. SoC Bus Bridge (Application Interface Module)
The SoC Bus bridging feature is added via an additional module called AIF which adds direct SoC bus connectivity with up to 8 DMA channels fully programmable from both the PCIe and SoC busses. The AIF Pprovides a higher-level interface that makes system integration easier than working at the TLP level. The AIF bridge Includes a DMA controller and other functions for straightforward interfacing of the coreis available for to standard SoC buses including. AMBA AMBA™ AXI, AHB and Wishbone versions are available. The Completion controller automatically handles read and write requests and sends completions if needed. The configurable DMA controller provides up to eight independent DMA channels. SupportThe core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available. VerificationThe core has been verified using Avery's PCI-Xactor verification tool, and has passed PCI-SIG certification. Interoperability has been verified with Intel, nVidia, VIA, and SIS chipsets, and PHYs from GeneSys Logic, Altera, and XIlinx have been successfully used. The core is in use by multiple customers. DeliverablesThe core is available in ASIC (synthesizable HDL) or FPGA (netlist) forms, and includes everything required for successful implementation:
On this page: Description | Implementation Results | Features | Applications | Block Diagram | Functional Description | Support | Verification | Deliverables Download PDF datasheets for more info: ASIC | Altera | Xilinx |
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We
conduct physical interoperability testing with systems and
boards from a variety of trusted vendors, including Agilent,
Altera, Dini Group, Hardi (now Synplicity) and Genesys Logic.
Please 
:
04/11/07
