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Dual CAN (CAN2) Bus Controller Core

On this page: Description | Features | Applications | Symbol Diagram | Block Diagram | Functional Description | Support | Verification | Deliverables

The development of increasingly complex microsystems requires the usage of a powerful field bus systems for distributed real-time networks. The CAN protocol has a wide acceptance in the field of serial communication.

The Dual CAN core is targeted to applications with two CAN core interfaces such as gateways. The Dual CAN bus controller core is described at the RTL system level which allows easy targeting of various technologies.

The Dual CAN bus core is founded on the basic CAN principle and meets all constraints of the CAN-specification 2.0B. For buffering of received or transmitted messages three 13-byte buffers are used. In practice no overload frames will be generated.

Features

• Supports CAN Specification 2.0B (Standard and Extended Data and Remote Frames)
• Two independent CAN cores with one host-controller interface
• Programmable data rate up to 1 mbps
• Programmable baud rate prescaler (up to 1/256)
• Programmable internal 27-bit acceptance filtering for both CAN’s
• 8-bit host-controller interface
• Application specific interface to the host-controller on request (e.g. AMBA-APB)
• Configurable interrupt sources
• Special “self test” logic for testcases inserted
• HDL design, complete synthesizable
• Link to commercial bus drivers (for instance PCA82C250T by Philips)
• Verified by the Bosch reference model
• The Dual CAN Controller synthesizes to approximate 8250 gates.

Applications

The CAN2 can be utilized in a variety of serial communication applications such as:

• gateways

Symbol Diagram

Block Diagrams

Functional Description

This section provides a short description of the Block Diagrams.

Interface Control

The Interface Control is responsible for handling the communications with the processor (parallel) side of the system. The msb of “addr” is responsible for which CAN is selected for accesses: addr[6]=0 ? CAN1, addr[6]=1 ? CAN2. CAN1 is selected by default. The logic is included into the “dual_can_core” as logic, not as an autonomous module.

Self Test Switch

The module controls the connections rxd and txd on the bus side. If the bit “self_tst” is set (only CAN1, addr 0x20) the core has no influence on the external bus. The two CAN cores CAN1 and CAN2 are connected together to be able to communicate with each other. If “self_tst” of CAN1 is low the CAN’s are connected to the external bus or buses only.

Host Controller Interface

The Interface block is responsible for handling the communications with the processor (parallel) side of the system. This block is needed only if wanted accesses with special conditions different from accesses as shown in figure 3 and 4. This block will be designed by request.

Memory Module (MM)

The Registers block consists of all configuration and control registers. The acceptance values will be stored in RAM’s. The module controls the accesses to the Memory block (Transmit and Receive Buffers) also. The Host controller accesses in memory mapped mode to the Memory Module.

Memory

The Memory consists of the Receive, Shadow and Transmit Buffers. It was implemented as distributed Xilinx RAM. It can be substitute by embedded RAM of the particular technology targeted.

Interface Management Logic (IML)

The Interface Management Logic controls the behavior of the whole core depending on the CPU commands (register settings into the memory module). The IML generates the addresses for the message buffers, controls the acceptance filtering (comparison of received identifier with the acceptance code bits, if acceptance mask bits enabled) and provides interrupts and status information to the host controller.

Bit Timing Logic (BTL), Prescaler

The BTL monitors the bus, synchronizes the internal actions to the bit stream on the CAN-bus. Hard synchronization will be execute if a “recessive-to-dominant“ bus line transition at the beginning of a message, Resynchronization on further “recessive-to-dominant“ transitions during the reception of a message. The timing registers (MM) controls the time segments to compensate for the propagation delay times and phase shifts and defines the sample point.

The BTL includes the Baud Rate Prescaler. The external system clock will be divided by a programmed value (from 2 to 256). The resulting period is called time quanta (TQ).

Bit Stream Processor (BSP)

The BSP converts the data streams from parallel to serial (from transmit buffer to the bus) and from serial to parallel (from bus to receive buffers).

Transceiver Logic (TCL)

The TCL consists of the protocol state machine. It controls all functions relating to receive and transmit frames in standard and extended format (specification 2.0B active):

• checking of received bits and transferring to the BSP
• generation of bits to transmit to the bus (ID-, RTR-, IDE-, DLC-, Data-, CRC-, …)
• arbitration
• stuff bit handling
• error handling
• generation of error and overload frames

Error Management Logic (EML)

The EML consists of counters for receive and transmit errors. The counters will be controlled depending of the kind of error (Bit Error, Stuff Error, Form Error, CRC Error, Acknowledgement Error).

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The Dual CAN controller has been implemented into Fraunhofer-IMS’ 1.0 micron double metal CMOS technology library and has been tested successfully. The core has also been certified by a Bosch reference model.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

• HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
• Sophisticated HDL Testbench including external FIFOs, buffers, models of interfaces, and the core
• Simulation script, vectors, expected results, and comparison utility
• Synthesis script (ASICs) or place and route script (FPGAs)
• Comprehensive user documentation, including detailed specifications and a system integration guide

On this page: Description | Features | Applications | Symbol Diagram | Block Diagram | Functional Description | Support | Verification | Deliverables

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This core developed by the bus interface experts at Fraunhofer Institute