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CAN Bus Controller Core

On this page: Description | Implementation Results | Features | Applications | Symbol Diagram | Block Diagram | Functional Description | Support | Verification | Deliverables

The development of increasingly complex microsystems requires the usage of powerful field bus systems for distributed real-time networks. The CAN protocol has a wide acceptance in the field of serial communication.

The CAN bus controller core is described at the RTL system level which allows easy targeting of various technologies.

The CAN bus core is founded on the basic CAN principle and meets all constraints of the CAN-specification 2.0B. For buffering of received or transmitted messages, three 13-byte buffers are used. In practice, no overload frames will be generated.

See representative implementation results (each in a new pop-up window):

Features

• Implementation of the Basic CAN specification
• No generated Overload Frames
• Receiving and transmitting of both identifiers (CAN specification 2.0B)
• Programmable data rate up to 1 mbps
• Programmable baud rate prescaler (up to 1/30)
• Application-specific interface to the host-controller
• Link to commercial bus drivers (for instance, PCA82C250T by Philips)
• Certified by Bosch reference model
• The CAN Controller synthesizes to approximate 6500 gates.
  

Applications

The CAN core can be utilized for a variety of serial communication applications including:

• Railway
• Automotive
• Industrial
  

Symbol Diagram

Block Diagram

Functional Description

The CAN bus core is founded on the basic CAN principle and meets all constraints of the CAN-specification 2.0B. For buff-ering of received or transmitted messages, three 13-byte buffer are used. In practice, no overload frames will be generated.

The Control Segment contains all necessary registers for controlling and configuring of the chip. The host controller is able to read and write the memory module as a conventional RAM in memory mapped mode.

The controller interface is interchangeable. All events on the data bus or in the controller are flagged as an interrupt to the host controller. Every interrupt may be enabled or disabled. The controller contains a 27-bit acceptance mask and a 27-bit acceptance code register.
The host controller interface is connected with the memory module by two 8-bit data buses and a 6-bit address bus. This allows for an easy interface exchange when using another host controller.

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The core has been verified through extensive simulation and rigorous code coverage measurements.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

• HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
• Sophisticated HDL Testbench
• Simulation script, vectors, and expected results
• Synthesis script (ASICs) or place and route script (FPGAs)
• Comprehensive user documentation, including detailed specifications and a system integration guide

On this page: Description | Implementation Results | Features | Applications | Symbol Diagram | Block Diagram | Functional Description | Support | Verification | Deliverables

Download PDF datasheets for more info: ASIC | Actel | Altera | Lattice | Xilinx

This core developed by the bus interface experts at Fraunhofer Institute