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C59016 16-bit Microprocessor Slice Core

On this page: Description | Implementation Results | Features | Applications | Symbol Diagram | Block Diagram | Functional Description | Support | Verification | Deliverables

The C59016 16-bit microprocessor slice core is a cascadable ALU intended for use in CPUs, peripheral controllers, and programmable microprocessors. The core includes a dual port RAM, ALU, shifter, register, decoding and multiplexer. The microinstructions of the C59016 allow for easy modeling of various microcontrollers.

See representative implementation results (each in a new pop-up window):

Features

• Independent and simultaneous access to two registers save machine cycles
• Eight function ALU
• Expandable – Any number of devices can be connected for wider bus structures
• Four status flags for Carry, Overflow, Zero and Negative
• Micro programmable
• The C59016 was developed in HDL and synthesizes to approximately 4,600 gates depending on the technology used
• Functionality based on the WaferScale WS59016

Applications

The C59016 core can be used for a variety of applications including:

• CPUs
• Peripheral controllers
• Programmable microprocessors

Symbol Diagram

Block Diagram

Functional Description

The C59016 core is partitioned into sections as shown in the block diagram and described below:

Dual Port RAM

The internal memory is a 16 bit by 16 Dual Port RAM. It is addressed for writing by the B Port and for reading by both the A and B Ports. The input data is defined by a microinstruction decoded from 3 bits of the 9-bit I Port.

RAM Latch

These latches store the outputs of the Dual Port RAM while the clock input is low. This eliminates any possible race conditions that could occur while new data is being written into the RAM.

Q Register

The Q register is driven from a three-input multiplexer. It will select no-shift, or shift-up or shift-down mode and clocked with the CP input.

ALU

The ALU can perform three binary arithmetic and five logic operations on the two 16-bit input words R and S, which are selected from multiplexers.

MicroInstructions

The I Port is internally decoded to define the flow of data to the above sections. I[2:0] decodes the ALU source operands. I[5:3] decodes the ALU function. And I[8:6] decodes the ALU destination.

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The C59016 core’s functionality was verified by means of a proprietary hardware modeler. The same stimulus was applied to a hardware model which contained the original four AMD 2901 and one AMD 2902 chips, and the results compared with the core’s simulation outputs.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

• HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
• Example testbench wrapper for post-route simulation
• Sophisticated HDL Testbench including external FIFOs, buffers, models of interfaces, and the core
• Simulation script, vectors, expected results, and comparison utility
• Synthesis script (ASICs) or place and route script (FPGAs)
• Comprehensive user documentation, including detailed specifications and a system integration guide

On this page: Description | Implementation Results | Features | Applications | Symbol Diagram | Block Diagram | Functional Description | Support | Verification | Deliverables

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