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C29116A 16-bit Microprocessor CoreOn this page: Description | Implementation Results | Features | Applications | Symbol Diagram | Block Diagram | Functional Description | Support | Verification | Deliverables The C29116A 16-Bit Microprocessor (C29116A) is a microprogrammable 16-bit bipolar microprocessor core whose architecture and instruction set is optimized for high-performance peripheral controllers, like graphics controllers, disk controllers, communi-cations controllers, front-end concentrators and modems. The device also performs well in microprogrammed processor applications. In addition to its complete arithmetic and logic instruction set, the C29116A instruction set contains functions particularly useful in controller applications; bit set, bit reset, bit test, rotate and merge, rotate and compare, and cyclic-redundance-check (CRC) generation. See representative implementation results (each in a new pop-up window): Features
ApplicationsThe C29116A can be used in a variety of microprogrammed processor and controller applications. Symbol Diagram
Block Diagram
Functional DescriptionThe C29116A is partitioned into modules as shown above and described below: RAMThe 32-word by 16-bit RAM is a single-port RAM with a 16-bit latch at its output. The latches are transparent when the clock (CP) input is high and latched when the clock is low. Data is written into the RAM while the clock is low if the IENN input is also low and if the instruction being executed defines the RAM as the destination of the operation. For byte instructions, only the lower eight RAM bits are written into; for word instructions, all 16 bits are written into. AccumulatorThe 16-bit accumulator is an edge-triggered register. The accumulator accepts data on the low-to-high transition of the clock input if IENN input is low and if the instruction be-ing executed defines the accumulator as the destination of the operation. For byte instructions, only the lower eight bits are written into; for word instructions, all 16 bits are written into. Data LatchThe 1t-bit data latch holds the data input to the C29116A on the bi-directional Y bus. The latch is transparent when the DLE input is high and latched when the DLE input is low. Barrel ShifterThe 16-bit barrel shifter is used as one of the ALU inputs. This permits rotating data from the RAM, the accumulator or the data latch up to 15 positions. In the word mode, the barrel shifter rotates a 16-bit word; in the byte mode, it ro-tates only the lower eight bits. ALUThe C29116A contains a 16-bit ALU with full carry look-ahead across all 16 bits in the arithmetic mode. The ALU is capable of operating on one, two or three operands, de-pending upon the instruction being executed. It has the ability to execute all conventional one and two operand op-erations, such as pass, complement, two’s complement, add, subtract, AND, NAND, OR, NOR, XOR, and XNOR. In addition, the ALU can also execute three-operand instruc-tions such as rotate and merge, and rotate and compare with mask. All ALU operation can be performed on either a word or byte basis, byte operations being performed on the lower eight bits only. The ALU produces three status outputs, C (carry), N (nega-tive) and OVR (overflow). The appropriate flags are generated at the byte or word level, depending upon whether the device is executing in the byte or word mode. The Z (zero) flag, although not generated by the ALU, de-tects zero at both the byte and word level. The carry input to the ALU is generated by the carry multi-plexer which can select an input of zero, one, or the stored carry bit from the status register, QC. Using QS as the carry input allows execution of multi-precision addition and subtractions. Priority EncoderThe priority encoder produces a binary-weighted code to indicate the locations of the highest order one at its input. The input to the priority encoder is generated by the ALU which performs an AND operation on the operand to be prioritized and a mask. The mask determines which bit lo-cations to eliminate from prioritization. Status RegisterThe status register holds the 8-bit status word. With the status register enable, SREN input low and the IENN input low, the status register is updated at the end of all instruc-tions, except NO-OP. The lower four bits of the status register contain the ALU status bits of zero (Z), carry (C), negative (N), and overflow (O). The upper four bits contain a link bit and three user-definable status bits (Flag1, Flag2, and Flag3). Instruction Latch and DecodeThe 16-bit instruction latch is normally transparent to allow decoding of the instruction inputs by the instruction decoder into the internal control signals. All instructions except im-mediate instructions are executed in a single clock cycle. SupportThe core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available. VerificationThe core has been verified through extensive simulation and rigorous code coverage measurements. DeliverablesThe core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:
On this page: Description | Implementation Results | Features | Applications | Symbol Diagram | Block Diagram | Functional Description | Support | Verification | Deliverables Download PDF datasheets for more info: ASIC | Altera | Xilinx |
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