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C2901 4-bit Microprocessor Slice Core

On this page: Description | Implementation Results | Features | Applications | Symbol Diagram | Block Diagram | Functional Description | Support | Verification | Deliverables

The C2901 4-Bit Microprocessor Slice core implements a cascadable ALU intended for use in CPUs, peripheral controllers, and programmable microprocessors. The core in-cludes a dual port RAM, ALU, shifter, register and multiplexer. The microinstructions of the C2901 allow for easy modeling of various microcontrollers.

The C2901 core can be customized to include:

• Larger data width
• Different RAM siz

The designed for reuse in ASICs and FPGAs. Deliverables include a testbench and everything needed to verify the core.

See representative implementation results (each in a new pop-up window):

Features

• Independent and simultaneous access to two registers save machine cycles
• Eight function ALU
• Expandable – Any number of devices can be connected for wider bus structures
• Four status flags for Carry, Overflow, Zero and Negative
• Microprogrammable
• The C2901 was developed in VHDL and synthesizes to approximately 2,500 gates depending on the technology used.
• Functionality based on the Advanced Micro Devices AM2901

Applications

The C2901 core can be used for a variety of applications. The C2901 core is used where simple microprogrammable controllers are required.

Symbol Diagram

Block Diagram

Functional Description

The C2901 core is partitioned into sections as shown in the C2901 Block Diagram and described below:

Dual Port RAM

The internal memory is a 4 bit by 16 Dual Port RAM. It is addressed for writing by the B Port and for reading by both the A and B Ports . The input data is defined by a microinstruction decoded from 3 bits of the 9 bit I Port.

RAM Latch

These latches store the outputs of the Dual Port RAM. They are clocked using the CP input.

Q Register

This section describes the internal register. It is se-lected using the Instruction input (I) and clocked with the CP input.

MicroInstructions

The I Port is internally decoded to define the flow of data to the above sections.

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The C2901 core’s functionality was verified by means of a proprietary hardware modeler. The same stimulus was ap-plied to a hardware model which contained the original AMD 2901 chip, and the results compared with the core’s simula-tion outputs.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

• HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
• Example testbench wrapper for post-route simulation
• Sophisticated HDL Testbench including external FIFOs, buffers, models of interfaces, and the core
• Simulation script, vectors, expected results, and comparison utility
• Synthesis script (ASICs) or place and route script (FPGAs)
• Comprehensive user documentation, including detailed specifications and a system integration guide

On this page: Description | Implementation Results | Features | Applications | Symbol Diagram | Block Diagram | Functional Description | Support | Verification | Deliverables

Download PDF datasheets for more info: ASIC | Altera | Xilinx