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FireWire 1394a IP Core C1394A IEEE-1394a Link Layer Controller Core

On this page: Description | Implementation Results | Features | Applications | Symbol | Block | Functional Description | Deliverables

The C139A core implements a link layer controller for the high-speed, high-bandwidth serial bus known commercially as FireWire(TM) and i.Link(TM).

The core conforms to the IEEE 1394-1995 and 1394a-2000 specifications. It is similar to the popular Texas Instruments TSB12LV32 General Purpose Link Layer Controller, but includes a 32-bit APB interface for easy connection with an AMBA(TM) bus host system. (AHB and other standard interfaces are also available.)

The C1394A can interface with any 1394-compliant physical layer (PHY) device, and includes easy-to-apply C-language software functions for all basic operations (options provide serial bus management and the transaction layer). It is FPGA-proven and has been exercised in a FireWire video camera demonstration system. ASIC results show it to require less than 39,000 gates.

The C1394A is a testable, microcode-free design developed for reuse in ASICs and FPGAs. It is fully synchronous and has no internal three-state buses. A complete verification environment helps designers verify the functioning and compliance of the core, and additional aids for system-on-chip simulation are available.

See representative implementation results (each in a new pop-up window):

Features

• Conforms to and implements all functionality of the IEEE 1394-1995 and IEEE 1394a-2000 standards
• Based on Texas Instruments TSB12LV32 General Purpose Link Layer controller
• Supports device data transmission of 400, 200 and 100 Mbps
• Includes 32-bit AMBA APB Slave microprocessor interface (other standard interfaces available)
• Fast, direct, 16-bit Data Mover interface supervises data flow to and from the external source
• Integrated receive and transmit buffers are configurable in size
• Validates data with 32-bit CRC generation for transmission and 32-bit CRC checking on reception
• Capable of Bus Manager, Isochronous Resource Manager and Cycle Master modes
• Able to receive all incoming isochronous traffic, and supports hardware filtering/acceptance for up to two streaming channels (more available upon request)
• Supports IEEE 1394 acceleration enhancement methods and the selective enabling/disabling of IEEE 1394a functions
• Uses Annex J standard to interface with any compliant PHY
• Dedicated software functions support all basic operations
• Additional software functions available as extra options for IEEE-1394a compliant Transaction Layer and Serial Bus Management (SBM)
• Debug feature introduces CRC errors during transmission
• Optional System-On-Chip simulation support provides aworking physical layer and emulates traffic and other nodes on the bus
• FPGA-proven, and offering competitive implementation results, e.g., 38,800 ASIC gates and 111 MHz host frequency
• Sophisticated self-checking Testbench (Verilog versions use Verilog 2001)

Applications

System integration is straightforward, as the core readily interfaces with any AMBA APB compliant host processor for control and to any 1394-1995 or 1394a-2000 compliant physical level (PHY) device for connection to a cable.

The 1394 bus facilitates the convergence of computers, peripherals, and consumer products. Typical applications include camcorders, televisions, digital cameras, external hard drives, scanners, and printers.

Symbol

Block

Functional Description

The operations of the C1394A core are divided into several blocks as shown in the previous diagram.

CFR – Control Function Registers

Incorporates the 32-bit host interface (AMBA APB) and control registers. It supports access to two internal FIFOs through which the host receives and transmits packets:

• GRF, the General Receive FIFO, and
• ATF, the Asynchronous Transmit FIFO.

The control logic of FIFOs is implemented inside the core. The storage of FIFOs is implemented as two separate blocks of dual port RAM connected externally to the core.

DMDR – Data Mover with Data Router

Supervises dataflow in the connected device and organizes data into packets. Independently supplies and receives data to the CFR processor interface for isochronous and asynchronous packets. For transmitting, it gets packets from the ATF or DM interface, and feeds this data into the LinkCore. For receiving, it gets packets from the LinkCore and feeds them into the GRF or DM interface.

The DMDR can be configured to receive any type of data traffic and has its own limited filtering feature. (This allows the core to check for additional user fields in data headers and decide whether the packet should go to the DM or to the GRF). Once the host processor configures it, the DMDR can handle data transmissions independent of that processor, notifying it only when an error is detected. The DMDR’s design also makes it straightforward to add application-specific modules that cooperate with the DM interface, such as a digital camera interface.

LinkCore

Responsible for executing all low-level transmissions and time-critical operations. This includes CRC calculation and checking, observing and generating protocol key events, and checking and generating acknowledge signals.

Link2PHY

The interface between LinkCore and the external Physical Layer (PHY). The core satisfies the Annex J standard and can operate with any physical layer device compliant with IEEE 1394-1995 and 1394a-2000 regulations.

Software

The dedicated software included with the core supports its basic operation. Optional software is available to provide the IEEE-1394a Transaction Layer and the Serial Bus Management (SBM) function. All the C1394A software is written in C so it can be readily ported to any processor.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

On this page: Description | Implementation Results | Features | Applications | Symbol | Block | Functional Description | Deliverables

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