Storage IP Core ATAIF ATA/IDE/ATAPI ATA-7 Interface Core
On this page: Description
| Implementation Results | Features
| Applications | Block Diagram
| Functional Description | Example
Application | Support | Verification
| Deliverables
Implements a host controller for non-volatile memory
devices using the parallel interface known as ATA (Advanced Technology
Attachment), IDE (Integrated Drive Electronics), and ATAPI (Advanced Technology
Attachment Packet Interface). Complies with standard ATA-7.
The core provides a simple interface to memory devices such as hard-disk
drives, DVD players, CDROM players/writers, Compact Flash storage, and
PC Card devices. It sup-ports PIO modes 0 to 4; Multi-word DMA modes 0,
1 and 2; Ultra ATA -33, -66, -100 and -133; and implements an interface
to the IDE bus.
Developed for easy reuse in ASIC and FPGA implementations, the core
is strictly synchronous, with positive-edge clocking, no internal tri-states,
and a synchronous reset; scan insertion is straightforward.
See representative implementation results (each
in a new pop-up window):
Features
- Complies with ATA-7 Standard
- Supports one or two IDE devices
- Supports synchronous Ultra ATA-33, -66, -100 and -133
- Configurable parameters allow easy tailoring of core to specific
application or implementation technology
- Programmable I/O modes:
0, 1, 2 and 4
- Multi-word DMA modes:
0, 1 and 2
- Generic SFR interface with configurable data bus: 8/16/32-bit
- Configurable Internal FIFO address bus width: min. 4-bit, no upper
limit
- Configurable transmission counter size: from 2- to 32-bit
- Use either the DMA Controller or the Master FIFO Controller for the
data transmission interface
- DMA Controller provides synchronous data transmission interface
- Master and slave mode
- Configurable data bus: 8/16/32-bit
- Configurable address bus: min. 8-bit, no upper limit
- Master FIFO Controller data transmission interface
- Configurable data bus width: 16- or 32-bit
- Easy direct connecting to CUSB2, CUSB2-OTG or USBHS-OTG-SD CAST
cores
- Transmit/Receive buffers operate as internal configurable FIFOs
- Configurable FIFO depth
- Configurable 16/32 bit data bus (when the Master FIFO Controller
interface is used)
-
Sophisticated self-checking Testbench (Verilog versions use Verilog 2001)
Applications
- IDE disk drive, CDROM player/writer & DVD player controllers
- Compact Flash and PC-Card readers
- Systems utilizing IDE/ATA and ATAPI drives for data storage including
notebook and desktop computers, servers, set-top boxes and test equipment
- Data acquisition systems
Block Diagram
Functional Description
The core is partitioned into modules as shown in the block diagram and
described below.
ATA Interface Controller
Contains the PIO, MDMA and UDMA state machines. These control the ATA
Interface working in PIO modes 0 to 4; Multi-word DMA modes 0, 1 and 2;
and Ultra ATA -33, -66, -100 and -133 modes.
Also parallel data CRC generation for UDMA transfers.
UDMA controller
Contains buffers for input data, used while the core executes Ultra
DMA transfers.
DMA Controller (optional)
Used for data transmissions, working as a master or a slave system data
bus (according to settings in the SFRs). Can be replaced by the Master
FIFO Interface Controller.
Master FIFO interface Controller (optional)
Controls the Master FIFO interface, which can be used to integrate the
ATA Interface Controller with USB controllers (e.g., CAST cores CUSB2,
CUSB2-OTG or USBHS-OTG-SD). Can be replaced by the DMA Controller.
Internal FIFO Controller
Has two buffers used for buffering transmit and receive data inside
the core. Generates read/write signals for two on-chip Dual-Port RAMs.
SFRs
Contains a set of Special Function Registers used for controlling the
core.
BUS Interface
Controls the microprocessor bus interface. It provides a synchronous
read/write interface to the SFRs that can be easily integrated with various
processor systems.
Example Application
Here the core is used to send data from system memory to a hard disk
drive. It uses the DMA Interface, and the CPU processes interrupts and
controls the settings.
Support
The core as delivered is warranted against defects for ninety days from
purchase. Thirty days of phone and email technical support are included,
starting with the first interaction. Additional maintenance and support
options are available.
Verification
The core has been verified through extensive simulation and rigorous
code coverage measurements.
Deliverables
The core is available in ASIC (synthesizable HDL) and FPGA (netlist)
forms, and includes everything required for successful implementation:
- HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
- Sophisticated self-checking Testbench (Verilog versions use Verilog 2001) including an example system design and
bus/behavioral model of interface stimulators
- Simulation script, vectors and expected results
- Synthesis script (ASICs) or place and route script (FPGAs)
- Comprehensive user documentation, including detailed specifications
and a system integration guide
On this page: Description
| Implementation Results | Features
| Applications | Block Diagram
| Functional Description | Example
Application | Support | Verification
| Deliverables
Download PDF datasheet: ASIC
| Altera | Xilinx
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