PDF datasheets: ASIC Altera Xilinx Related information: News Releases 06/04/07 CAST Offers PCI Express Model, Highlights APS 32-bit Processor Cores at DAC 2007 04/16/07 E2v Chooses 32-bit Processor for Upcoming Products: the Cortus APS3 Core from CAST 05/15/06 CAST Energizes Small, Fast Systems with New Low-Power, 32-Bit Processor Cores Related Cores APS2 High-Performance 32-bit Processor Core APS-DSP Digital Signal Coprocessor For more information: contact Sales @ CAST Customer applications: E2v Chooses 32-bit Processor for Upcoming Products: the Cortus APS3 Core from CAST  April 16, 2007

APS3 32-Bit, 32-bit Code-Optimized Microprocessor Core

On this page: Description | Implementation Results | Features | Applications | Block Diagram | Functional Description | Support | Verification | Deliverables

Implements a 32-bit RISC processor designed for small chip area, low power, and compact application code in a variety of embedded systems applications. It is especially intended for 8/16-bit upgrade applications, aimed at systems requiring more than a microcontroller but less than a typical 32-bit processor.

The APS3 is a modern RISC design with a 5-7 stage pipelined, load/store architecture. Its advanced features include out-of-order instruction completion, and it supports a variety of peripherals and memory interfaces. A patented coprocessor interface makes it easy to extend the instruction set and optimize the processor for any specific application; barrel shifter and multiplier coprocessors are available.

Optimized to yield extremely dense application code, the APS3 uses a mix of 16-bit and 32-bit long instructions, and also interfaces efficiently with 16-bit memories.

Designed from the start for efficient high-level programming with C and C++, the processor includes a complete tool set adapted from the GNU Project. It includes a carefully optimized compiler, a graphical debugger that connects through a JTAG link or via the serial port on a PC, a comprehensive instruction set simulator (ISS), and a standard library of C routines for embedded systems. Third parties such as MicroCross, Inc. are also moving to adapt their advanced development environments to the APS3.

The APS3 is more compact than many 8-bit processors — requiring as few as 9,500 gates¹ — and is suitable for ASICs and most FPGAs. It is significantly faster than the microcontrollers it replaces, and more frugal with power, its CPU needing as little as 24 µW/MHz¹ . The core has been successfully implemented in FPGAs, and has been rigorously verified through thousands of test cases and many different applications.

See representative implementation results (each in a new pop-up window):

Features

• Modern RISC architecture, with one instruction per cycle, including load and store
• Latency hiding through out-of-order instruction completion
• 32-bit ALU, with sixteen 32-bit registers
• 16- and 32-bit long instructions allow greater code density, efficient 16-bit memory interfaces
• Pipelined, five to seven stages
• Harvard architecture; cross bar switch for single-bus interface
• Optional instruction cache is two-way-set-associative, with eight kilobyte capacity
• Four GB of addressable memory
• Support for byte and half-word data access (signed/unsigned)
• Course-grained clock gating on pipeline stages for low power
• Built-in sleep mode
• Optional integrated barrel shifter
• Patented coprocessor interface for easy functional extension: multiplier, cryptographic processor, and multiply and accumulate (MAC) coprocessors available

Competitive Benchmarks

• Code-Dense: can save 40% code memory space over APS2
• Fast: speed rating of 0.55 DMIPS/MHz¹
• Small: as low as 9,500 ASIC gate equivalents¹
• Frugal: CPU energy consumption as little as 24 µW/MHz¹

Development Environment

• High-level programming in C and C++
• Customized GNU tool set:
• GCC Compiler optimizes code
• GDB source code Debugger with graphic front end
• Linker, source code and library maintenance tools
• Instruction Set Simulator (ISS)
• Integrated with Debugger; runs graphically if desired
• Key peripherals models
• Debugging connection through JTAG interface or PC serial port
• Instruction set optimized for GCC compiler and embedded applications code: 140 instructions of fixed-length for fastest processor speed

¹ Minimum configuration, using TSMC .09 µm process.

Applications

With its 16/32-bit processing, easy programming, and high code density, the APS3 is well suited to encryption, wireless communications, and other systems requiring considerable application code, as well as for hand-held, battery-driven, and other power-critical systems.

Block Diagram

Functional Description

The APS3 is designed for energy-efficient high performance with the extremely compact programming code.

The core is a modern RISC design with a load/store architecture, and uses five to seven pipelined stages. Out-of-order instruction completion hides memory latency, while fully-vectored interrupts enable the low latency required in real-time embedded applications. A configurable, programmable priority interrupt controller is built in to manage interrupts.

A mix of 16- and 32-bit long instructions enable more compact code without significantly reducing processor speed or increasing the total number of instructions that need must be executed.

The core’s patented coprocessor interface makes it easy to extend the instruction set and optimize the processor for any specific application, such as increasing the speed of a digital signal processing algorithm. Barrel shifter and multiplier coprocessors are available.

The core supports a variety of standard memory interfaces, and comes with a number of useful peripherals. These include a UART, Timer, and General Purpose IO unit. Power-saving features include a built-in sleep mode that has instruction stops with external clock handling, and interrupt handling for clock restarts.

Designed specifically as a processor for the 8/16-bit micro-controller upgrade market, the APS achieves economy by eliminating typical 32-bit processor features that usually go unused in these applications. It was not designed, for example, to support virtual memory, floating point instructions, or different memory address modes, nor to run a complex OS with multiple protection rings. For its intended embedded applications, however, the APS3 needs relatively little application code space, and is one of the fastest and least power hungry such solutions available.

Development Environment

The APS3 was designed for efficient high-level programming using C and C++, and a C library for embedded applications and a complete tool set of GNU Project based development tools is included to facilitate this. The tools include a customized GCC compiler, GDB debugger, and more. The debugger connects through a JTAG interface (four pins), or through the serial port on a PC.

An Instruction Set Simulator (ISS) and various peripheral models also come with the core. The ISS is integrated with the debugger, can run in a graphical mode if desired, and has features that help it better match RTL simulations.

Third party partners are also moving to tailor their advanced development environments to APS products, most notably MicroCross, Inc.

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The core has been verified through extensive simulation and rigorous code coverage measurements. Demonstration units have also been implemented and evaluated; initial ASIC projects are underway.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

• HDL RTL source code
• Customized GNU tool set for Windows or Linux, including compiler, debugger, linker, source code and library maintenance tools, and instruction set simulator with models. C library for embedded applications
• Sophisticated self-checking HDL Testbench including everything needed to test the core
• Simulation scripts, vectors, expected results; Synthesis scripts
• Comprehensive user documentation, including detailed specifications and a system integration guide with example system

On this page: Description | Implementation Results | Features | Applications | Block Diagram | Functional Description | Support | Verification | Deliverables

Download PDF datasheets for more info: ASIC | Altera | Xilinx

This core developed by the processor experts at Cortus, SA