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AES32-C
32-bit Datapath AES Encrypt/Decrypt Core

On this page: Description | Implementation Results | Applications | Features | Block Diagram | Functional Description | Support | Verification | Export Permits | Deliverables

The AES32-C core implements Rijndael encoding in compliance with the FIPS-197 Advanced Encryption Standard. It can be programmed to either encrypt or decrypt 128-bit blocks of data, with a 128-bit, 192-bit or 256-bit cipher key.

The AES32-C core has a 32-bit datapath size, meaning four clock cycles are required to load/unload each 128-bit plaintext/ciphertext block. The core requests the externally calculated Round Key values while it processes an input block. An optional Key Schedule memory buffer can store the pre-computed Round Key values prior to encryption or decryption. A Key Expander is also provided as an optional module to automatically fill the Key Schedule buffer. Since the core has a 32-bit datapath and all internal operations are performed on 32-bit words, 44/52/60 clock cycles are required to encrypt or decrypt a block of data with a 128/192/256-bit cipher key respectively. The same number of cycles is required by the Key Expander module for key expansion.

The AES32-C core is equipped with fully-stallable input and output interfaces. These enable the user’s application to stop the input stream according to a data arrival rate, or to stop the output stream when the core is not able to receive data.

The core has been evaluated in a variety of technologies, and is available optimized for ASICs or FPGAs. Representative results show it to produce a competitive implementation, running at 300 MHz and requiring just 12,400 gates in a .18 µm ASIC process.

See representative implementation results (each in a new pop-up window):

Applications

The core is suitable for a variety of applications, including:

• Secure networking routers
• Wireless communications
• Encrypted data storage
• Secure video surveillance systems
• Electronic financial transactions

Features

• Conforms to the Advanced Encryption Standard (AES), FIPS PUB 197
• Supports both Encryption and Decryption, programmable during operation
• Supports 128/192/256-bit Cipher keys
• Processes each 128-bit block in 44/52/60 clock cycles for 128/192/256-bit cipher keys respectively
• Fully-stallable input and output interfaces, ideal for streaming applications
• Various cipher modes are supported, selectable during core configuration (prior to synthesis):
• ECB (Electronic Codebook)
• CBC (Cipher Block Chaining)
• CFB (Cipher Feedback)
• OFB (Output Feedback)
• CTR (Counter)
• Optional Key Schedule memory buffer for storage of Round Key values
• Optional Key Expansion module
• Optimized design for ASIC or FPGA implementations
• Robust verification environment includes bit-accurate software model (BAM)
• Scan-ready design architecture

Block Diagram

Functional Description

Prior to any encryption or decryption operation, the Round Key values for the current cipher key must be calculated. To save processing time, an optional Key Expander component is available that can simplify this task.

Then the user has to provide the Round Key values according to the core’s requests, or store them to the optional Key Schedule memory buffer. In this case the core can encrypt or decrypt a stream of blocks of data, until a new cipher key has to be used and the Round Key values be recalculated. The cipher key size and whether the core will encrypt or decrypt the block of data entered, are controlled by the state of input control signals, and may be changed on the beginning of each block without any performance penalty.

The core features a powerful input / output interface, that permits fully-stallable data streaming through the core. The application receiving the output of the core can pause output data generation arbitrarily. In a similar way, the application that feeds data to the input of the core can arbitrarily pause the data stream to it. The core can also stall the application to its input, when it is busy processing, or when the output cannot receive any more processed data.

The core can be configured before implementation to operate in ECB, CBC, CFB, OFB, CTR modes.  Additional modes can be supported on request. 

Support

The AES32-C core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

The AES32-C core has been verified through extensive simulation and rigorous code coverage measurements. It has also been verified in a prototyping FPGA board platform.

Export Permits

Strong encryption technology is governed internationally by export regulations. Immediate export of the core is permitted to the following countries:

Please contact CAST to discuss delivery to other destinations; approval is subject to the applicable export licenses being granted. Please note that licensees are responsible for complying with the applicable requirements for re-export of electronics containing strong encryption technology.

Deliverables

The core is available in ASIC (synthesizable HDL) and FPGA (netlist) forms, and includes everything required for successful implementation:

• HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
• Synthesis script (ASICs) or place and route script (FPGAs)
• Simulation script, vectors and expected results
• Sophisticated self-checking Testbench (Verilog versions use Verilog 2001)
• Software (C++) Bit-Accurate Model
• Comprehensive user documentation, including detailed specifications and a system integration guide

On this page: Description | Implementation Results | Applications | Features | Block Diagram | Functional Description | Support | Verification | Export Permits | Deliverables

Download PDF datasheets for more info: ASIC | Altera | Xilinx

 This core developed by the encryption experts at Alma Technologies S.A