Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs. See the video and image compression Family Page for a media compression overview.

 H.264 Video Decoders
Low Latency Constrained
  Baseline Profile

Low-Power Constrained
  Baseline Profile

 H.265 HEVC Decoders
Main Profile

Companion Cores
Image Processing
WDR/HDR
CAMFE Camera Processor
Network Stacks
40G UDPIP Stack
1G/10G UDPIP Stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
IEEE 802.1AS Time Sync.
   Stack

IEEE 802.1Qav & 802.1Qbv
   Stack

• MPEG Transport Stream
  Mux

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

JPEG-LS
Lossless & Near-Lossless
Encoder
Decoder

Lossless Data Compression
GZIP Compressor
GUNZIP Decompressor
GZIP Reference Designs
    • for Intel FPGAs
    • for Xiinx FPGAs

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

Flash Controllers
Parallel Flash
Parallel Flash for AHB
Universal Serial NOR/NAND
   Flash for AHB

Legacy Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

SPI
Octal/Quad/Dual/Single SPI
XIP & DMA for AHB
XIP for AHB
Quad SPI
XIP & DMA for AHB
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
Master/Slave VIP
I2C
Master  • Slave

These encryption cores make it easy to build security into a variety of systems.

AES
AES, programmable
  CCM, GCM, XTS
Key Expander

DES
DES single
DES triple

Hash Functions
SHA-3 (Keccak)
SHA-256
SHA-1
MD5

<<< Return to Newsletters page

CAST logo

CAST COREspondence

The IP newsletter from CAST, Inc. — December 19, 2016

The IP Industry: Mature Yet Ever-Expanding

This month we participated in both the oldest IP industry event—D&R’s IP-SoC —and the newest—REUSE 2016. This reflects the state of IP itself: the art and science of developing, packaging, and licensing great IP products is quite mature, but the applications and importance of IP are growing without apparent limit.

GZIP is a good example. It has long been familiar as a file compressor for desktop computer users. But today the high-performance, low-latency, area-efficient IP cores we offer are enabling new applications of GZIP in reducing power, memory, and bandwidth requirements from tiny IoT devices to massive data centers.

The CAN bus is another good example. We first introduced CAN IP in 2003. But with the boost in capacity and performance brought by the recent CAN FD “Flexible Data” spec, uses of CAN are growing rapidly, both automotive and in other areas like industrial. One-third of our CAN sales for 13 years have been in 2016, and the rate continues to grow.

These new applications for familiar technologies are exciting, but it’s the mature aspect of IP—the art and science—that make them viable in today’s complex systems. Get in touch and let’s talk about how the mature IP CAST offers can help you expand into new, competitive technologies.

Nikos Zervas, CEO, +1 201.391.8300

CAN Bus Bundle: Design IP + Verification IP

Avery/CAST logosIn November we announced a new CAN IP bundle with our partner Avery Design Systems: license the CAN FD Bus Controller design IP from us, and get a month's use of Avery’s excellent CAN-Xactor verification IP package for free.

Available now through CAST, the CAN 2.0 and FD bundle with 30-day free VIP license is pre-configured to give system developers an immediate, “out of the box” way to evaluate the CAN IP against all applicable industry specifications. An easy, cost-effective license offered through CAST or Avery then allows developers to conveniently use the same VIP suite to verify the correct operation of the CAN bus as their system development progresses.

Read more in our CAN Bundle press release.

Customer Story: CEITEC Chooses 8051

CEITEC SA logoCEITEC S.A. in Brazil is one of the most advanced semiconductor design and manufacturing firms in Latin America. They’re known for RFID chips for tracking things—animals, vehicles, blood products, and more—and for developing and manufacturing custom ASICs.

CEITEC has begun work on a new embedded security controller platform, and needs a processor that’s fast yet very low-power. Easy code development and system integration—and very loIt has loverall risk—are also important factors. They chose the MCS®51-compatible R8051XC2 IP Core we offer.

Marcus Kindel, ASIC design engineer and project manager for CEITEC, said:

“Our unique mission is to develop innovative microelectronic solutions meeting the needs of Brazil and the overall market, while also contributing to national development. This 8051 IP provides key features like an efficient power management unit, on-chip debug, and user-configurable peripherals, and combined with its high performance and ease of use satisfies our specific design requirements. Moreover, CAST’s long 8051 track record and effective support give us great confidence in this choice.”

We’ll be following their progress and will report when they deploy their completed system.

Conference Presentations: IoT, Video, and GZIP

We participated in two December IP industry events.

IP-SOC 2016 logoIP-SoC 2016 in Grenoble marked Design and Reuse’s twentieth year. We found this key gathering of the IP industry as worthwhile and stimulating as ever. See the interview with our chairman Hal Barbour to the right. Our Senior VP Bill FInch also gave a somewhat contrarian talk on “Back to the Future. The End of IoT.”

REUSE 2016 logo We were also pleased to be early sponsors of REUSE 2016. This inaugural event just for IP users and developers proved to be quite worthwhile, and it's expected to return next year. We presented two papers there.

Our CEO Dr. Nikos Zervas spoke on a topic close to his technical heart: “Choosing the Right IP Cores for Low-Latency Video Streaming.”

Our VP of Sales Meredith Lucky also spoke at REUSE, on modern applications of a familiar technology in “Using GZIP Data Compression to Reduce Power Consumption in IoT Devices.”

How To:
Easily Monitor, Control, and Upload Firmware to Your Device Over SPI

Problem  You are designing a micro-controller or similar device and want to use a simple serial interface like SPI to upload firmware on boot, or to update the firmware from time to time. Sounds easy. But are you ready to write a boot-loading driver to do this over a typical SPI slave port? Things get more complicated if you have no non-volatile memory on chip, and even worse if an external host needs to monitor some register values and change others at run time.

Solution   Plug our new SPI2AHB SPI to AHB-Lite Bridge IP core into your AHB bus, and get full access to the on-chip AHB bus via an SPI slave port.

The SPI2AHB Bridge implements a simple over-SPI protocol to receive specially-formed commands via the SPI slave port. It then translates the commands to read or write transactions on the AHB master port. So, in practice, you get full access to the device’s entire on-chip AHB bus address space via the simple SPI port!

The Bridge operates on its own, and presents itself as an AHB master, so no new drivers or overhead for your on-chip CPU are involved. You can even put the on-chip CPU to sleep while the external host uploads firmware or initializes registers in your peripherals.

More complex schemes would require an AHB matrix or arbitration of the AHB -Lite bus, but for the simple needs we’ve described, the SPI2AHB Bridge is the way to go.

In our next issue, read how you can easily gain access to your internal AHB bus via an Ethernet connection.

In this Issue:

•  Mature Growth

•  CAN Bundle

•  CEITEC 8051

•  Presentations

•  How To: SPI Bridge

•  Product Updates

•  Interview

•  Upcoming Events

•  Product Lists


Recent Product Updates

New core:
SPI2AHB
SPI to AHB-Lite Bridge
Part of our AMBA Bus Peripherals IP group, this Bridge core gives you access to an internal AHB bus via a simple SPI interface. See the How To tip to the left for one of its applications.

Updated cores:

H264-D-BP Low-Latency AVC/H.264 Baseline Profile Decoder Core

H264OIP-HDE H.264 Video Over IP – HD Encoder Subsystem

AES-P Programmable Advanced Encryption Standard Core

CAN-CTRL CAN 2.0 & CAN FD Bus Controller Core


Interview

Hal Barbour video interview

At D&R's IP-SoC event in Grenoble, our Chairman Hal Barbour sat down to talk with D&R President Gabrielle Saucier about newer—and older—IP that CAST customers are using. Watch the five-minute video.


Upcoming Events

Embedded World 2017 logo

Embedded World 2017
March 14–16, 2017 Nuremberg, Germany
Booth 2-529

MOCAST 2017 logo

Modern Circuits and Systems Technologies (MOCAST)
4 - 6 May 2017, Thessaloniki Greece Our CEO Dr. NIkos Zervas is an invited keynote speaker, addressing “Ultra Low Latency Video Streaming.”



Brochure with Products List

Download list of CAST IP Cores & Platforms

Download a brochure with product list PDF:
Letter size
A4 size
 

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