Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs. See the video and image compression Family Page for a media compression overview.

 H.264 Video Decoders
Low Latency Constrained
  Baseline Profile

Low-Power Constrained
  Baseline Profile

 H.265 HEVC Decoders
Main Profile

Companion Cores
Image Processing
CAMFE Camera Processor
Network Stacks
40G UDPIP Stack
1G/10G UDPIP Stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
IEEE 802.1AS Time Sync.

IEEE 802.1Qav & 802.1Qbv

• MPEG Transport Stream

JPEG Still & Motion

Lossless & Near-Lossless

Lossless Data Compression
GZIP Compressor
GUNZIP Decompressor
GZIP Reference Designs
    • for Intel FPGAs
    • for Xiinx FPGAs

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers

Device Controllers
smart card reader

Flash Controllers
Parallel Flash
Parallel Flash for AHB
Universal Serial NOR/NAND
   Flash for AHB

Legacy Peripherals
DMA Controllers
8237, 82380
16450S, 16550S, 16750S

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Octal/Quad/Dual/Single SPI
Quad SPI
Single SPI
SPI to AHB-Lite

Master/Slave Controller
Master/Slave VIP
Master  • Slave

These encryption cores make it easy to build security into a variety of systems.

AES, programmable
Key Expander

DES single
DES triple

Hash Functions
SHA-3 (Keccak)

CAST logo

CAST COREspondance

The IP newsletter from CAST, Inc. — October 10, 2013

Reusability Evolves: Cores to Subsystems and More

At CAST's founding in 1993, we did well building and selling simulation models. Soon, though, we entered (started?) the age of reusability by answering customer requests for "synthesizable simulation models," i.e., early IP cores. We never looked back.

Fast forwarding a couple of decades, reusing individual cores is now standard operating procedure, and savvy designers are embracing the greater productivity gains made possible by reusing bigger chunks of IP.

It's the "subsystem IP" era, and demand is growing for larger, pre-integrated and pre-verified packages with essential software, all ready to drop in to perform some complete SoC function. We're introducing another such subsystem ourselves, with the new Video Over IP solution described below.

Customers sometimes ask about the difference between an "IP subsystem" and an "IP platform" (we have several of those, too, e.g., for the BA2x family with AXI).

A platform is not just a bigger subsystem, but rather a complete hardware/software combination that enables actual application development. A processor platform, for example, gives you a framework into which you might drop one or more subsystems—like bluetooth connectivity or video streaming—to complete your unique SoC.

Defining terms like this might seem an academic exercise, but the consistency that eventually arises helps simplify your task of understanding and selecting IP products. After all, we don't get many searches for "synthesizable simulation models" these days.

What do you think about this higher-level reusable IP, and what forms of it are you looking to use? Drop me a line or give me a call.

-- Hal Barbour, President, +1 201.391.8300 ext. 111


New Video Over IP H.264 Streaming Subsystem

Our new H.264 Video Over IP Subsystem is a powerful, efficient, and cost-effective solution for easily adding video streaming to the many SoCs that need it today.

It combines the H.264 High-Profile Video Encoder Core we source from Alma Technologies with our own RTP and UDP/IP Hardware Stacks to give you high-quality video compression and fast transmission over Ethernet or Wi-Fi. This coupling of ultra-low latency video encoder with near-zero latency hardware stacks enables streaming with a negligible delay of 5ns or less.

Flexible interfaces and a stand-alone option for processor-free operation make the versatile subsystem easy to integrate, while a suite of hardware reference design kits speed up development. Our customization services can save you even more time, building in different video inputs, network controllers, processing modules, or even JPEG or JPEG 2000 compression to exactly satisfy your specific needs.

Check the details online or give us a call (+1 201.391.8300) to see if it might be the right solution for your streaming needs.

ht be the right solution for your streaming needs.


White Paper: Understanding—and Reducing—Latency in Video Compression Systems

Latency in a video system is the delay between when a frame is captured by a camera and when it is played back on a display. Achieving low latency is the goal of many systems, such as for video conferencing and even more so for in remote surgery.

video latency illustration

The factors that determine latency, though, aren't always obvious. In most systems, it is actually the video encoder near the beginning of the process that ends up having the biggest impact on overall delay.

Our new white paper defines and explains the basics of video latency and gives designers advice on choosing IP to minimize it. Click to read it online: Understanding—and Reducing—Latency in Video Compression Systems.

Initial response to the white paper has been very positive—we seem to have touched a nerve—so we're planning to hold a free webinar expanding on the topic in November. Email us if you might be interested in attending, and let us know what specific latency issues you've had to grapple with.

In this Issue:

•  Reusability Evolves

•  New H.264 Subsystem

•  Video Latency

•  Upcoming Events

•  Recent Events

•  Multi-CAN Core

•  Product Updates

•  Current Products

Upcoming Events

Visit CAST partner AST at CDNLive Israel 2013. October 14, 2013 at the David Intercontinental Hotel Tel Aviv, Israel

D&R IP-SoC Conference
November 6-7, 2013
Grenoble, France

Recent Events

Design and Reuse's founder Gabrielle Saucier graciously interviewed CAST's Nikos Zervas at IP-SoC Day in Beijing, China, September 12, 2013. Watch & read about the interview on our blog.

New Multi-CAN Capability

The CAN bus continues to be extremely popular, especially among engineers designing automotive systems, but also for industrial (e.g. the CANopen and DeviceNet protocols), aviation (e,g. the ARINC-825 and CANaerospace protocols), and marine (e.g. the NMEA 2000 protocol) applications.

We recently upgraded the CAN 2.0 core we offer with a multi-CAN capability. This significantly reduces integration effort whenever a single processor needs to control multiple CAN nodes on a single or on multiple CAN buses.

Watch for an upcoming blog post describing the core's new advantages, and meanwhile check out the CAN 2.0 Bus Con-troller Core datasheet.

Recent Product Updates

New & updated products:
•  H264OIP-HDE Video
    Over IP Subsystem

    Bus Controller Core

BA2x Processor Updates
•  renamed PIP-BA22 to
•  CoreMarks improved

8051s source transitioned from Evatronix to Cadence (acquisition)

Current Products

Download list of CAST IP Cores & Platforms

Download a product list PDF: Letter size

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Copyright © 2013, CAST, Inc. CAST is a trademark of CAST, Inc. All other trademarks are the property of their respective owners.
CAST, Inc., 50 Tice Blvd., Suite 340, Woodcliff Lake, NJ 07677 +1.201.391.8300


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