Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs. See the video and image compression Family Page for a media compression overview.

 H.264 Video Decoders
Low Latency Constrained
  Baseline Profile

Low-Power Constrained
  Baseline Profile

 H.265 HEVC Decoders
Main Profile

Companion Cores
Image Processing
CAMFE Camera Processor
Network Stacks
40G UDPIP Stack
1G/10G UDPIP Stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
IEEE 802.1AS Time Sync.

IEEE 802.1Qav & 802.1Qbv

• MPEG Transport Stream

JPEG Still & Motion

Lossless & Near-Lossless

Lossless Data Compression
GZIP Compressor
GUNZIP Decompressor
GZIP Reference Designs
    • for Intel FPGAs
    • for Xiinx FPGAs

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers

Device Controllers
smart card reader

Flash Controllers
Parallel Flash
Parallel Flash for AHB
Universal Serial NOR/NAND
   Flash for AHB

Legacy Peripherals
DMA Controllers
8237, 82380
16450S, 16550S, 16750S

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Octal/Quad/Dual/Single SPI
Quad SPI
Single SPI
SPI to AHB-Lite

Master/Slave Controller
Master/Slave VIP
Master  • Slave

These encryption cores make it easy to build security into a variety of systems.

AES, programmable
Key Expander

DES single
DES triple

Hash Functions
SHA-3 (Keccak)

CAST logo

CAST COREspondance

The IP newsletter from CAST, Inc. — March 30, 2011

Growing Team, New Cores

Our success in the competitive IP business is due in part to a unique aspect of the CAST approach: we complement our internally developed IP with IP from the very best development experts around the world, and establish deep, enduring partnerships with them. And whether the IP is created by CAST or by a partner, a single license and support infrastructure is provided to customers worldwide.

CAST sells Trilinear IPWe're now adding a new such partner to the CAST team: Trilinear Technologies.

Trilinear has focused on image and video processing IP for challenging applications since 2005. We'll be bringing Trilinear's deep suite of silicon-proven IP cores to CAST customers worldwide, and also tapping the company's development systems, application or integration services, and more.

We'll be merging the new Trilinear-sourced products into the CAST product line over the next few months. This will give us new video decoders, image scalers, and more, to complement our existing video and image IP family.

As with all CAST products, CAST people will be your main interface for IP selection help, integration advice, and front-line support. But we'll also have the rich depth of Trilinear's engineering group available to help you when needed.

Please join me in welcoming Trilinear to the CAST team. And let me know if you may have a need for any of these upcoming new cores.

-- Hal Barbour, President, +1 201.391.8300 ext. 111

ONFi NAND Flash Controller Improvements

Systems using powerful functions like our H.264 video encoder need especially good memory interfaces. We're constantly working to improve the SDIO Host and other controllers we offer, and are about to announce new features for our NAND Flash controller.

This fifth-generation core conforms to ONFi 2.2 and runs significantly faster than the previous version.

A new configurable BCH engine does rapid, on-the-fly error correction of up to 64 bits per page, allowing high-bandwidth access to the memory even in the presence of errors. Several options further reduce software overhead and unload the system processor, including AES encryption, bad-block management, and multi-page transfer, all in hardware.

Our NANDFLASH-CTRL datasheet page already includes the new features; watch for our press announcement coming soon.

New Application Interface Core for FPGA
PCI Express Hard Macros

One of the challenges working with PCI Express is understanding and managing the Transaction Packet Layer.

We previosly developed a higher-level, Application Interface (AIF) for our PCIe controller cores that simplifies integration by managing the TPL for you. (See our Embedded Computer Design article PDF for details).

Now the PCIEXPAIF Interface Core we recently announced gives you this same easier development and integration when using the PCIe hard macros available from Altera® and Xilinx®.

Embedding an extensible DMA engine and relieving you of the need to directly manage the low-level activity, this core helps you focus at the more productive application level. Once you connect your PCIe controller through the AIF to your SoC bus, you're ready to access PCIe just like any other memory-mapped module.

On the sytem bus side, the core supports the 32- and 64-bit versions of the open source Wishbone Bus, and the AMBA® AHB™, AXI™ and AXI4 buses.

The Altera version is compatible with Altera Cyclone® IV GX, Arria® II GX, Stratix® IV GX, and Stratix V GX devices.

The Xilinx version is compatible with Virtex®-5, Virtex-6 and Spartan®-6 devices.

We can also support for additional buses, vendors, or device families: just call (+1 201.391.8300) or email to let us know what you need.


In this Issue:

Upcoming Events

47th DAC, June2010

ChipEx Israel
May 3–4, 2011
Visit CAST in the AST booth for details on our latest products.

CAST cores at DesignCon 2011

SoCIP China
May 24–25, 2011
Visit our booth for a live IP demon-stration and to discuss all your IP requirements.

CAST IP at DAC 2011

48DAC, the 48th Design Automation Conference
June 6 - 8, 2011
San Diego Convention Center
Booth 2217

Recent News

CAST joins the HSIA in Greece

We're proud to join the Hellenic Semiconductor Industry Association (HSIA).

User Feedack

Pixel Velocity uses our JPEG core is their Pixel Video Fusion™ high-def security cameras. They said:

“CAST provided a robust JPEG solution that allowed Pixel Velocity to reduce its development time to get to market faster. CAST provided all the necessary tools to validate the solution in software, accelerating the development process of Pixel Velocity personnel.

The integration of the CAST JPEG core with the Pixel Velocity system was easy.The CAST personnel were always available to offer support and answer questions.”

How are you using CAST IP? What do you think of working with us? Email and let us know.

Recent Website/Product Updates

Video & Image IP

  • JPEG 2000 Application Platform — datasheet posted
  • H264-MP-E and H264-BP-E — datasheet improvements

Bus & Interface Cores

  • PCIEXPAIF — new core

Memory Controller IP

  • SDIO-HOST — feature updates
  • NANDFLASH-CTRL — new version

Follow Us on Twitter

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Copyright © 2011, CAST, Inc. CAST is a trademark of CAST, Inc. All other trademarks are the property of their respective owners. CAST, Inc., 50 Tice Blvd., Suite 340, Woodcliff Lake, NJ 07677 +1.201.391.8300



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