CAST Releases TSN Ethernet Subsystem for Automotive and Industrial Applications
DESIGN AUTOMATION CONFERENCE—SAN FRANCISCO, CALIFORNIA, USA, June 29, 2018
IP provider CAST concluded Design Automation Conference (DAC) week by announcing the only available IP subsystem implementing the latest IEEE standards for Time Sensitive Networking (TSN) over Ethernet. The TSN Ethernet Subsystem integrates IEEE standard Time Synchronizing, Time Shaping, and a special low-latency Ethernet MAC to save automotive and industrial system designers significant time and expense when implementing TSN Ethernet. read more ...
CAST Adds JPEG-LS Decoder to Lossless Image Compression IP Core Suite
WOODCLIFF LAKE, NJ USA, June 12, 2018
CAST adds a JPEG-LS Decoder for a scalable and extremely low-power, small-area, highly-efficient encode/decode solution for numerical- or visually-lossless compression of high quality images and video streams. read more ...
Resurgence in 8051 Microcontroller Applications Drives New IP Cores Sales for CAST
WOODCLIFF LAKE, NJ USA, May 25, 2018
CAST 8051 MCU IP sales reach a surprisingly high level, as designers find the 8051 IP cores' low power consumption, small size, great reliability, easy integration and development, and royalty-free licensing make them an excellent solution for IoT and other modern applications. read more ...
Achronix Release — CAST and Achronix Enable Processing from Data Center to the Edge with Lossless Compression IP
Santa Clara, Calif., April 10, 2018
CAST, a member of the Achronix Partner Program, has ported its GZIP IP core for lossless data compression to Achronix eFPGA devices. read more ...
CAST and Accelize Make GZIP Compression Instantly Available via Cloud-Based FPGA Accelerators
WOODCLIFF LAKE, NJ USA, April 09, 2018
Hardware accelerated GZIP data compression IP from CAST is now available for use on a time or data basis through the new AccelStore and supporting cloud accelerator ecosystem from Accelize. read more ...
CAST Introduces GZIP Accelerator Through New Intel FPGA Data Center Acceleration Ecosystem
WOODCLIFF LAKE, NJ USA, October 17, 2017
This GZIP lossless data compression reference design is available for the Intel Programmable Acceleration Card (Intel PAC) with Intel Arria 10 GX FPGA. It uses the ZipAccel-C GZIP/ZLIB/Deflate Compression IP Core, and has been designed with QuickPlay® in partnership with Accelize®. The GZIP Accelerator Function is part of the expanded Intel® FPGA Design Solutions Network (DSN), of which CAST is an early member. read more ...
CAST Drives Automotive IP Forward with New AVB/TSN Ethernet and SAE J2716 Sensor Bus Cores plus CAN-FD Time-Stamping
WOODCLIFF LAKE, NJ USA, June 13, 2017
New IEEE 802.1AS AVB/TSN and SENT/SAE J2716 Cores now available; CAN/CAN-FD Controller Core now supports AUTOSAR-compliant time-stamping read more ...
CAST Adds DO-254 Avionics Interface Cores though New Partnership with Nolam
Woodcliff Lake, NJ, June 01, 2017
DO-254 compliant avionics bus IP cores now available from CAST — MIL-STD 1553, ARINC 429, and ARINC 825 — proven in the field and sourced from new CAST partner Nolam Embedded Systems. read more ...
Novatek Reduces TV Boot Time with Data Decompression IP Core from CAST
WOODCLIFF LAKE, NJ USA, May 16, 2017
Novatek Microelectronics Corp., a customer of semiconductor IP provider CAST, Inc., has applied a data decompression IP core to achieve a major consumer benefit: significantly reduced start-up delay in digital televisions. read more ...
Geon Secure Execution Processor Brings Royalty-Free Protection to IoT Devices
IoT DevCon, Santa Clara, CA, April 26, 2017
The Geon Secure Execution Processor builds cryptographic protection of critical code and data into a low-power, high-performance, BA2x 32-bit processor IP core. read more ...
This presentation given at the REUSE 2017 conference describes how reliable silicon and software IP with the right features is key for the timely design of today's complex automotive electronics.
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Warren and Nikos talk about the IP industry and how CAST has been successful in it by satisfying customer needs with unique IP. Filmed at the REUSE IP conference and trade show in December, 2016.
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Latest White Paper
In this paper we look at how IP cores for hardware GZIP/Deflate based data compression and decompression can significantly reduce power consumption in large categories of IoT devices. We will further show through multiple examples that the power reductions to be gained far exceeds the active and idle power usage of the additional compression and decompression cores.
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