Recent News and Updates

News Releases

• CAST Expands Popular UDP/IP Networking Cores Line
  Woodcliff Lake, NJ, May 23, 2019
  CAST's 10G and 40G UDP/IP Hardware Protocol Stack cores for lean Internet Protocol networking get an increase up to 32 channels, and soon faster, 100G versions of these IP cores. read more ...
• New SoC Security Platform Announced by CAST and Beyond Semiconductor
  Embedded World — Nuremberg, Germany, February 25, 2019
  Announcing the GEON Security Platform, an essential suite of interoperating IP modules for thoroughly protecting SoCs, with relatively easy deployment and sharing of encryption and other resources for great efficiency. It includes Secure Boot, Firmware Encryption, Secure Debug, and a Hardware Secure Module (HSM) read more ...
• TSN IP Core making devices fit for real-time Ethernet
  Nuremberg, Germany, November 27, 2018
  Time-Sensitive Networking (TSN) is a set of standards allowing for the timed and prioritized transmission of real-time critical messages over standard Ethernet hardware. With the TSN IP Core, developers at Fraunhofer IPMS provide equipment manufacturers and operators the opportunity to make their devices fit for new TSN standards. Fraunhofer IPMS will be presenting the possibilities of the TSN IP Core to members of the specialist public in Hall 7a, Booth 246 at this year's SPS IPC Drives event from 27-29 November in Nuremberg. read more ...
• TSN Ethernet Subsystem Available from CAST Proven at IIC and LNI Plugfests
  WOODCLIFF LAKE, NJ, USA, September 05, 2018
  The Time Sensitive Networking (TSN) Ethernet Subsystem available from CAST has successfully undergone the real-world-like functional and interoperability testing of IIC and LNI plugfests. read more ...
• CAST Releases TSN Ethernet Subsystem for Automotive and Industrial Applications
  DESIGN AUTOMATION CONFERENCE—SAN FRANCISCO, CALIFORNIA, USA, June 29, 2018
  IP provider CAST concluded Design Automation Conference (DAC) week by announcing the only available IP subsystem implementing the latest IEEE standards for Time Sensitive Networking (TSN) over Ethernet. The TSN Ethernet Subsystem integrates IEEE standard Time Synchronizing, Time Shaping, and a special low-latency Ethernet MAC to save automotive and industrial system designers significant time and expense when implementing TSN Ethernet. read more ...
• CAST Adds JPEG-LS Decoder to Lossless Image Compression IP Core Suite
  WOODCLIFF LAKE, NJ USA, June 12, 2018
  CAST adds a JPEG-LS Decoder for a scalable and extremely low-power, small-area, highly-efficient encode/decode solution for numerical- or visually-lossless compression of high quality images and video streams. read more ...
• Resurgence in 8051 Microcontroller Applications Drives New IP Cores Sales for CAST
  WOODCLIFF LAKE, NJ USA, May 25, 2018
  CAST 8051 MCU IP sales reach a surprisingly high level, as designers find the 8051 IP cores' low power consumption, small size, great reliability, easy integration and development, and royalty-free licensing make them an excellent solution for IoT and other modern applications. read more ...
• Achronix Release — CAST and Achronix Enable Processing from Data Center to the Edge with Lossless Compression IP
  Santa Clara, Calif., April 10, 2018
  CAST, a member of the Achronix Partner Program, has ported its GZIP IP core for lossless data compression to Achronix eFPGA devices. read more ...
• CAST and Accelize Make GZIP Compression Instantly Available via Cloud-Based FPGA Accelerators
  WOODCLIFF LAKE, NJ USA, April 09, 2018
  Hardware accelerated GZIP data compression IP from CAST is now available for use on a time or data basis through the new AccelStore and supporting cloud accelerator ecosystem from Accelize. read more ...
• CAST Introduces GZIP Accelerator Through New Intel FPGA Data Center Acceleration Ecosystem
  WOODCLIFF LAKE, NJ USA, October 17, 2017
  This GZIP lossless data compression reference design is available for the Intel Programmable Acceleration Card (Intel PAC) with Intel Arria 10 GX FPGA. It uses the ZipAccel-C GZIP/ZLIB/Deflate Compression IP Core, and has been designed with QuickPlay® in partnership with Accelize®. The GZIP Accelerator Function is part of the expanded Intel® FPGA Design Solutions Network (DSN), of which CAST is an early member. read more ...