New Video Compressor and Camera Processor Cores Expand CAST’s IP Line
WOODCLIFF LAKE, NJ USA, January 18, 2017
CAST, Inc. recently added two media processing cores to its extensive line of semiconductor intellectual property cores and subsystems: H.264-E-HIS - High 10 Intra Profile Encoder and CAMFE - Camera Front-End Processor. read more ...
CEITEC chooses 8051 IP from CAST for Embedded Security Controller Platform
WOODCLIFF LAKE, NJ USA, December 01, 2016
CEITEC S.A., one of the most advanced semiconductor design and manufacturing firms in Latin America, has chosen an 8051-compatible microcontroller IP core from CAST, Inc. for its new embedded security controller platform. read more ...
CAN Bus Design IP from CAST Now Bundles In Avery Verification IP
WOODCLIFF LAKE, NJ AND TEWKSBURY, MA, November 01, 2016
CAN 2.0/FD Bus Controller IP core with 30-day free verification IP license: CAST and Avery Design Systems have partnered to deliver a proven, cost-effective, ready-to-run design and verification package for automotive and other applications of the CAN Bus. read more ...
CAST Expands Streaming Video IP Line with Motion JPEG Subsystem
WOODCLIFF LAKE, NEW JERSEY, October 19, 2016
Motion JPEG (MJPEG) provides a leaner, lower-power video solution than video codecs like H.264 when moderate levels of compression are required. System designers can exploit the benefits of Motion JPEG for video streaming in many Internet of Things (IoT) and other applications. read more ...
Accelerate SHA-3 Cryptographic Hash Processing with New Hardware IP Core
WOODCLIFF LAKE, NEW JERSEY, October 05, 2016
Intellectual property core supports the latest standard for protecting the integrity of electronic transmissions, Secure Hash Algorithm-3 (SHA-3), in a flexible, high-throughput, area-efficient hardware accelerator. read more ...
Cache Controller Core from CAST Augments Cache-Less 32-bit Processors
WOODCLIFF LAKE, NEW JERSEY, September 19, 2016
Cache Controller Core from CAST Augments Cache-Less 32-bit Processors read more ...
CAST and PLDA GROUP demonstrate x86-compliant high compression ratio GZIP acceleration on FPGA, accessible to non-FPGA experts using the QuickPlay Software Defined FPGA development tool
SAN JOSE, CA — Flash Memory Summit, August 09, 2016
Easily deploy fast GZIP compression to save data center power and bandwidth using the ZipAccel IP core from CAST with the QuickPlay FPGA board configuration system from PLDA Group. read more ...
CAST Introduces Low-Power, Ultra-HD Capable Video Compression Cores
WOODCLIFF LAKE, NJ, July 21, 2016
CAST's newest video and image compression IP cores feature JPEG, H.264, and HEVC encoders and decoders with low power consumption, tiny silicon area, and scaleable, 4K/8K high performance. read more ...
CAN FD Controller IP Core Excels Through Third Plug Fest Testing
WOODCLIFF LAKE, NJ, June 16, 2016
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CAST Licenses GZIP Core to Tier 1 Wireless Chipset Vendor
Design automation Conference — Austin, TX, June 07, 2016
Customer is using GUNZIP data compression IP core to save power and resources via firmware compression within an LTE chipset. read more ...
I/O design simplified for Flex Logix EFLX users with qualified I2C, SPI, and UART IP cores
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CAST Chairman Hal Barbour talks about recent IP successes with D&R's Gabrielle Saucier: automotive (CAN FD), data compression, 8051s, and 32-bit BA2 processors.
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Latest White Paper
In this paper we look at how IP cores for hardware GZIP/Deflate based data compression and decompression can significantly reduce power consumption in large categories of IoT devices. We will further show through multiple examples that the power reductions to be gained far exceeds the active and idle power usage of the additional compression and decompression cores.
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