Geon Secure Execution Processor Brings Royalty-Free Protection to IoT Devices
IoT DevCon, Santa Clara, CA, April 26, 2017
The Geon Secure Execution Processor builds cryptographic protection of critical code and data into a low-power, high-performance, BA2x 32-bit processor IP core. read more ...
CAST Becomes Member of ESD Alliance
REDWOOD CITY, CA, April 18, 2017
The Electronic System Design Alliance (ESD Alliance), an international association of companies providing goods and services throughout the semiconductor design ecosystem, today announced Semiconductor intellectual property (SIP) provider CAST, Inc. has become a member. CAST, Inc. will lend its IP expertise to SIP working group to help chart direction. read more ...
CAST Expands CAN Bus Solutions Suite with New PHY Daughter Card
WOODCLIFF LAKE, NJ USA, March 14, 2017
Announced at Embedded World: new daughter card for connecting a system using a CAN controller to the physical CAN bus expands CAST's CAN IP solutions set. read more ...
New Video Compressor and Camera Processor Cores Expand CAST’s IP Line
WOODCLIFF LAKE, NJ USA, January 18, 2017
CAST, Inc. recently added two media processing cores to its extensive line of semiconductor intellectual property cores and subsystems: H.264-E-HIS - High 10 Intra Profile Encoder and CAMFE - Camera Front-End Processor. read more ...
CEITEC chooses 8051 IP from CAST for Embedded Security Controller Platform
WOODCLIFF LAKE, NJ USA, December 01, 2016
CEITEC S.A., one of the most advanced semiconductor design and manufacturing firms in Latin America, has chosen an 8051-compatible microcontroller IP core from CAST, Inc. for its new embedded security controller platform. read more ...
CAN Bus Design IP from CAST Now Bundles In Avery Verification IP
WOODCLIFF LAKE, NJ AND TEWKSBURY, MA, November 01, 2016
CAN 2.0/FD Bus Controller IP core with 30-day free verification IP license: CAST and Avery Design Systems have partnered to deliver a proven, cost-effective, ready-to-run design and verification package for automotive and other applications of the CAN Bus. read more ...
CAST Expands Streaming Video IP Line with Motion JPEG Subsystem
WOODCLIFF LAKE, NEW JERSEY, October 19, 2016
Motion JPEG (MJPEG) provides a leaner, lower-power video solution than video codecs like H.264 when moderate levels of compression are required. System designers can exploit the benefits of Motion JPEG for video streaming in many Internet of Things (IoT) and other applications. read more ...
Accelerate SHA-3 Cryptographic Hash Processing with New Hardware IP Core
WOODCLIFF LAKE, NEW JERSEY, October 05, 2016
Intellectual property core supports the latest standard for protecting the integrity of electronic transmissions, Secure Hash Algorithm-3 (SHA-3), in a flexible, high-throughput, area-efficient hardware accelerator. read more ...
Cache Controller Core from CAST Augments Cache-Less 32-bit Processors
WOODCLIFF LAKE, NEW JERSEY, September 19, 2016
Cache Controller Core from CAST Augments Cache-Less 32-bit Processors read more ...
CAST and PLDA GROUP demonstrate x86-compliant high compression ratio GZIP acceleration on FPGA, accessible to non-FPGA experts using the QuickPlay Software Defined FPGA development tool
SAN JOSE, CA — Flash Memory Summit, August 09, 2016
Easily deploy fast GZIP compression to save data center power and bandwidth using the ZipAccel IP core from CAST with the QuickPlay FPGA board configuration system from PLDA Group. read more ...
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CAST's Meredith Lucky talks with editor John Blyler about innovative uses customers find for GZIP compression, trends in IP, and the success of the first REUSE IP-focused trade show.
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Latest White Paper
In this paper we look at how IP cores for hardware GZIP/Deflate based data compression and decompression can significantly reduce power consumption in large categories of IoT devices. We will further show through multiple examples that the power reductions to be gained far exceeds the active and idle power usage of the additional compression and decompression cores.
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