Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs. See the video and image compression Family Page for a media compression overview.

 H.264 Video Decoders
Low Latency Constrained
  Baseline Profile

Low-Power Constrained
  Baseline Profile

 H.265 HEVC Decoders
Main Profile

Companion Cores
Image Processing
WDR/HDR
CAMFE Camera Processor
Network Stacks
40G UDPIP Stack
1G/10G UDPIP Stack
• Hardware RTP Stack
  – for H.264 Encoders
  – for H.264 Decoders
  – for JPEG Encoders
IEEE 802.1Qav & 802.1Qbv
   Stack

• MPEG Transport Stream
  Mux

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

JPEG-LS
Lossless & Near-Lossless
Encoder
Decoder

Lossless Data Compression
GZIP Compressor
GUNZIP Decompressor
GZIP Reference Designs
    • for Intel FPGAs
    • for Xiinx FPGAs

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

Flash Controllers
Parallel Flash
Parallel Flash for AHB
Universal Serial NOR/NAND
   Flash for AHB

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Automotive Buses
CAN

CAN 2.0/FD controller
CAN FD Reference Design
CAN Bus VIP
LIN
LIN Bus Master/Slave
SENT/SAE J2716
Tx/Rx Controller
Automotive Ethernet
TSN Ethernet Subsystem

Avionics/DO-254 Buses
MIL-STD 1553
ARINC 429
ARINC 825 CAN

SPI
Octal/Quad/Dual/Single SPI
XIP & DMA for AHB
XIP for AHB
Quad SPI
XIP & DMA for AHB
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
I2C
Master  • Slave

These encryption cores make it easy to build security into a variety of systems.

GEON SoC Security
GEON Security
    Platform

Encryption Primitives
AES
AES, Programmable
  CCM, GCM, XTS
Key Expander
DES
Single, Triple

Hash Functions
SHA
SHA-3 (Keccak)
SHA-256
SHA-1
MD5
MD5

Other Posts & News

Recent Blog Posts

Recent News

See all the blog posts or news items

by CAST, Inc.

TIME SENSITIVE NETWORKING — An Introduction to TSN

White Paper

By Dr. Andreas Weder, Fraunhofer IPMS

Introduction

TSN Ethernet illustration by Fraunhofer IPMS

Ethernet has been equally established as a dependable wired solution in both computer and automation networks. The open standard allows terminals to be quickly and simply connected as well as easily scaled to exchange data with relatively inexpensive hardware. 
 
Ethernet was, however, not originally designed to meet the requirements posed by automation technology, particularly in regards to guaranteed and real-time communication. Therefore, various bus systems in automation have evolved using Ethernet on a physical level while implementing proprietary real-time protocols on top. These systems often lead to the exclusive use of the network infrastructure as well as vendor dependencies. Such networks handling time-critical data traffic are today separated from networks directing less-critical data traffic in order to eliminate reciprocal negative interference.
 
In the future, Industry 4.0 applications will require increasingly more consistent Ethernet networks.  Such networks can only be produced at great cost with the traditional structure. Time-Sensitive networking (TSN) provides a solution aiming to change these current conditions. 

Real-time Communication 

Guarantees regarding cycle times and fluctuations in cycle times are prerequisite for a range of application fields in automation, including, for example, drive, control, and conveyor technology. The data transfer times demanded in these application fields are significantly less than 1 ms.

In addition to these applications requiring “hard” real-time capability, other applications such as process automation implement “soft” real-time capability with longer cycle times. Nevertheless guaranteed latencies are required for these applications as well. Various real-time communication methods such as EtherCat or Profinet IRT have been specially developed to provide guaranteed cycle times. Although they are based on conventional Ethernet, they are not compatible with each other. This incompatibility has resulted in fragmented networks.

Download the PDF to continue with: 

• Why TSN?
• Important Core Elements 
• TSN IP Core on FPGA Basis
• Summary and Outlook

Or go to the TSN_CTRL TSN Ethernet Subsystem product page.

 

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