Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs.
• See the video and image compression Family Page

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

JPEG LS
Encoder
Lossless & Near-Lossless

Lossless Data Compression
GZIP Compressor
GUNZIP Decompressor
GZIP Reference Designs
    • Intel Accelerator
    • Xiinx PCIe Board

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

NOR Flash Controllers
Parallel Flash for AHB
SPI Flash
Octal, XIP for AHB
Quad, XIP for AHB
Quad, XIP for AXI

Legacy Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Ethernet MAC
• 1G eMAC Controller

Network Stacks
40G UDPIP Stack
1G/10G UDP/IP stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
• MPEG Transport Stream
  Encapsulator

Automotive Buses
CAN

CAN 2.0/FD controller
CAN FD Reference Design
CAN PHY Daughter Card
CAN Bus VIP
LIN
LIN Bus Master/Slave
SENT/SAE J2716
Tx/Rx Controller
Automotive Ethernet
IEEE 802.1AS Hardware
   Protocol Stack

Avionics/DO-254 Buses
MIL-STD 1553
ARINC 429
ARINC 825 CAN

SPI
Octal SPI
XIP for AHB
Quad SPI
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
Master/Slave VIP
I2C
Master  • Slave

Data Link Controllers
• SDLC & HDLC
UARTs
16450S, 16550S, 16750S

PCI — Target
32-bit, 32-bit multi, 64-bit
PCI — Master
32-bit, 32-bit multi, 64-bit
PCI — Host Bridge
32 bit, 32 bit - AHB
32 bit & device - AHB

These encryption cores make it easy to build security into a variety of systems.

AES
AES, programmable
  CCM, GCM, XTS
Key Expander

DES
DES single
DES triple

Hash Functions
SHA-3 (Keccak)
SHA-256
SHA-1
MD5

CAST Blog Posts for WHITE-PAPER Category

  • Innovative Energy Savings Using GZIP IP Within IoT Devices (D&R IP-SoC 2015 Paper)

    Innovative Energy Savings Using GZIP IP Within IoT Devices 
(D&R IP-SoC 2015 Paper)
    In this paper we look at how IP cores for hardware GZIP/Deflate based data compression and decompression can significantly reduce power consumption in large categories of IoT devices. We will further show through multiple examples that the power reductions to be gained far exceeds the active and idle power usage of the additional compression and decompression cores.
  • White Paper — Data Compression for Low Energy IoT Connectivity

    White Paper — Data Compression for Low Energy IoT Connectivity
    Most IoT devices use considerable energyfor  wireless data transmission.Using losslaess data compression within the device archtiecture can help, as shown here through examples using the GZIP IP core available from CAST.
  • White Paper — Firmware Compression for Lower Energy and Faster Boot in IoT Devices

    White Paper — Firmware Compression for Lower Energy and Faster Boot in IoT Devices
    IoT devices that employ code shadowing can enjoy significant energy savings by using efficient hardware code compression. The compressed application code needs a smaller NVM device for long-term storage, and the system consumes significantly less time and energy reading the compressed code from the system's non-volatile memory (NVM) into the on-chip SRAM. The code can be decompressed in-line (as it is read out of the NVM), at the cost of practically negligible additional delay or energy usage.
  • 8051 Interrupt Latency: Designing with Modern 8-bit MCUs

    8051 Interrupt Latency: Designing with Modern 8-bit MCUs
    Today's 8051-compatible MCUs use advanced architectural designs to run fast, use little energy, and exhibit extremely low latency. This makes them ideal for Internet of Things (IoT), wearable electronics, and other popular applications. Here we look closely at the factors that determine processor latency, and how the right 8051 designs can do a better job than many 32-bit processors.
  • White Paper: Understanding—and Reducing—Latency in Video Compression Systems

    White Paper: Understanding—and Reducing—Latency  in Video Compression Systems
    Achieving the least possible delay in a video capture, streaming, and display system can be surprisingly affected by the specific H.264 encoder near the beginning of that flow. Read this white paper to learn more about what determines latency, and how to pick the best encoder for achieving low latency in your systems.
  • Consider Code Density when Choosing Embedded Processors

    Consider Code Density when Choosing Embedded Processors
    The code density of a processor's instruction set architecture (ISA) can have a great impact on how power-efficient that processor will be in real-world SoCs.
  • 8051s in the Spectrum of Microcontroller Choices

    For the right sorts of systems, 8-bit 8051 microcontrollers can still be a hero in today's mobile, feature-happy world.
  • Chip Replacement with IP and FPGAs: 68000 Processor Example

    For some projetcs, the best way to cope with an obsolete processor chip is to implement that processor in an FPGA using an IP core. We explore the issues, using 68000 replacement as an example.

 

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