NewsJPEG Encoder IP Core from CAST gets Rate Control Options, Faster FPGAs

Woodcliff Lake, NJ, June 4, 2012 — Semiconductor IP provider CAST, Inc. today announced functional and performance improvements for the JPEG Encoder IP core it provides.

System designers now have a choice of two rate control options that allow application-specific tuning of the JPEG compression function:

• Buffer-Limited, Block-Based Rate Control minimizes on-chip memory for buffering and transmission bandwidth with good-quality image results.
• Motion JPEG Video Oriented Rate Control maximizes the quality of results for Motion JPEG streams, while still using hardware resources efficiently.

“Image compression simply means ‘JPEG’ to the uninitiated, but this is very far from a ’one size fits all’ technology,” said Nikos Zervas, vice president of marketing for CAST. “The specific compression algorithm and the choice of processing options within it can make a huge difference on quality, bandwidth, memory requirements, performance, and energy consumption. We pride ourselves on helping customers understand, determine, and deploy the optimum encoder for their particular system.”

The JPEG Encoder core now runs on the latest Altera® and Xilinx® FPGAs, at up to 400 MSamples/sec. This means a single encoder core can process 1080p@60fps video on low-cost Altera Cyclone-V and Xilinx Artix™-7 devices, or Digital Cinema 4k@30fps on higher-end devices like Altera Stratix® V and Xilinx Virtex®-7 FPGAs. The core has also been tested with the new Xilinx Vivado™ toolset, for better productivity when working with Xilinx devices.

CAST offers and supports the broadest and deepest set of image compression IP cores and subsystems available, including JPEG, Scalado Speedtags JPEG, 12/8-bit Extended JPEG, lossless LJPEG and JPEG-LS, and JPEG 2000. Video compression cores from CAST include multiple H.264 profiles, MPEG2, and DV. The JPEG and H.264 IP cores are sourced from Technology Partner Alma Technologies.