Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs. See the video and image compression Family Page for a media compression overview.

 H.264 Video Decoders
Low Latency Constrained
  Baseline Profile

Low-Power Constrained
  Baseline Profile

 H.265 HEVC Decoders
Main Profile

Companion Cores
Image Processing
WDR/HDR
CAMFE Camera Processor
Network Stacks
40G UDPIP Stack
1G/10G UDPIP Stack
• Hardware RTP Stack
  – for H.264 Encoders
  – for H.264 Decoders
  – for JPEG Encoders
IEEE 802.1Qav & 802.1Qbv
   Stack

• MPEG Transport Stream
  Mux

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

JPEG-LS
Lossless & Near-Lossless
Encoder
Decoder

Lossless Data Compression
GZIP Compressor
GUNZIP Decompressor
GZIP Reference Designs
    • for Intel FPGAs
    • for Xiinx FPGAs

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

Flash Controllers
Parallel Flash
Parallel Flash for AHB
Universal Serial NOR/NAND
   Flash for AHB

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Automotive Buses
CAN

CAN 2.0/FD controller
CAN FD Reference Design
CAN Bus VIP
LIN
LIN Bus Master/Slave
SENT/SAE J2716
Tx/Rx Controller
Automotive Ethernet
TSN Ethernet Subsystem

Avionics/DO-254 Buses
MIL-STD 1553
ARINC 429
ARINC 825 CAN

SPI
Octal/Quad/Dual/Single SPI
XIP & DMA for AHB
XIP for AHB
Quad SPI
XIP & DMA for AHB
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
I2C
Master  • Slave

These encryption cores make it easy to build security into a variety of systems.

GEON SoC Security
GEON Security
    Platform

Encryption Primitives
AES
AES, Programmable
  CCM, GCM, XTS
Key Expander
DES
Single, Triple

Hash Functions
SHA
SHA-3 (Keccak)
SHA-256
SHA-1
MD5
MD5

related links

Recent news summary page

Download this release (pdf)

See the USBHS-OTG-MPD Hi-Speed On-The-Go Controller for Multiple Peripheral Devices datasheet

NewsCAST Expands USB OTG Line with New Multi-Port IP Core

Efficient, flexible USB Hi-Speed On-The-Go core features integrated DMA controller for higher performance and easier system design

March 7, 2005, MUNICH, Germany — DATE — Semiconductor intellectual property (IP) provider CAST, Inc. today announced a new IP core that implements a dual-role host/device controller in conformance with the On-The-Go (OTG) supplement to the USB 2.0 specification.

USB OTG builds on the popularity of USB (Universal Serial Bus) by making it even easier to connect digital products. Whereas USB needs a computer host to manage the connection to one or more devices (a master-slave protocol), OTG gives every device enough host capabilities so they can be directly interconnected. Users can, for example, connect their OTG-equipped camera directly to a printer for photos or to a cell phone for Internet sharing, without the use of a computer. (See www.everythingusb.com/usbonthego for more information.)

In host mode, the new CAST USBHS-OTG-MPD core supports hi-speed hubs, and multiple low- full-, and hi-speed peripheral devices. In device mode, the core supports full-speed and hi-speed data transfers. The core’s integrated Direct Memory Access (DMA) controller handles essential data management functions, while its hardware implementations of the Host Negotiation Protocol, Session Request Protocol, and other critical functions add to its efficiency. Standard USB transceivers (PHYs) work with the core through its UTMI+ interface, and system integration is straight forward using the core’s AMBA™ AHB slave interface (other interfaces are available). The core’s competitive hardware implementation requires just 45,000 gates and runs at 200 MHz in an 0.18 micron ASIC process.

Available in April for ASICs or FPGAs, the USBHS-OTG-DPD core includes a complete test environment with a behavioral PHY model that helps designers verify the functioning and compliance of the core. It joins CAST’s single-port USB OTG core, which has already passed USB-IF certification.

The USBHS-OTG-DPD core was developed by CAST partner Evatronix SA, based in Poland (www.evatronix.pl). The core’s pricing varies by configuration and license type; contact CAST for details.

About CAST Incorporated

CAST provides over 100 popular and standards-based IP cores for ASICs and FPGAs. Privately owned and operating since 1993 with a focus on making IP practical and affordable, CAST has established a reputation for high-quality IP products, simple licensing, and responsive technical support. The company is headquartered near New York City, partners with IP developers around the world, and works with select sales consultants and distributors throughout Europe and Asia.

# # #

CAST, Inc.,
11 Stonewall Court, Woodcliff Lake, NJ 07677 USA
Tel: 201/391-8300            info@cast-inc.com
Fax: 201/391-8694           www.cast-inc.com

CAST is a trademark of CAST, Inc.
All other trademarks are the property of their respective owners.

 

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