Aldec’s Active-HDL™ and Riviera-PRO™ HDL simulators offer a complete FPGA or ASIC verification environment, including effective design creation, and high-performance RTL and gate-level simulation. They use a high-speed, mixed-language simulation engine that supports VHDL, Verilog®, SystemVerilog and SystemC/C/C++. They also feature optimal waveform toolsets, ultra-fast debugging tools, code coverage and a set of advanced verification methods. Learn more about Aldec’s simulators and additional products at