Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Secure Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs. See the video and image compression Family Page for a media compression overview.

 H.264 Video Decoders
Low Latency Constrained
  Baseline Profile

Low-Power Constrained
  Baseline Profile

 H.265 HEVC Decoders
Main Profile

Companion Cores
Image Processing
WDR/HDR
CAMFE Camera Processor
Network Stacks
40G UDPIP Stack
1G/10G UDPIP Stack
• Hardware RTP Stack
  – for H.264 Encoders
  – for H.264 Decoders
  – for JPEG Encoders
IEEE 802.1Qav & 802.1Qbv
   Stack

• MPEG Transport Stream
  Mux

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

JPEG-LS
Lossless & Near-Lossless
Encoder
Decoder

Lossless Data Compression
GZIP Compressor
GUNZIP Decompressor
GZIP Reference Designs
    • for Intel FPGAs
    • for Xiinx FPGAs

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

Flash Controllers
Parallel Flash
Parallel Flash for AHB
Universal Serial NOR/NAND
   Flash for AHB

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Automotive Buses
CAN

CAN 2.0/FD controller
CAN FD Reference Design
CAN Bus VIP
Automotive Ethernet
TSN Ethernet Subsystem
CAN-to-TSN Gateway
LIN
LIN Bus Master/Slave
LIN Bus VIP
SENT/SAE J2716
Tx/Rx Controller

Avionics/DO-254 Buses
MIL-STD 1553
ARINC 429

SPI
Octal/Quad/Dual/Single SPI
XIP & DMA for AHB
XIP for AHB
Quad SPI
XIP & DMA for AHB
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
I2C
Master  • Slave

These encryption cores make it easy to build security into a variety of systems.

GEON SoC Security
GEON Security
    Platform

Encryption Primitives
AES
AES, Programmable
  CCM, GCM, XTS
Key Expander
DES
Single, Triple

Hash Functions
SHA
SHA-3 (Keccak)
SHA-256
SHA-1
MD5
MD5

Other Posts & News

Recent Blog Posts

Recent News

See all the blog posts or news items

by CAST, Inc.

Silicon IP Quality: Is this still an issue?

by Article

Nikos Zervas, CAST, Inc.

Also posted to the GSA IP Working Group Blog

Silicon IP, or SIP, has become essential to the semiconductor supply chain and is the cornerstone for most complex nanometer SoC designs. Over the past 15 years, SIP has shortened development cycles, reduced development cost and risk, enabled complex SoC design, and allowed design groups to focus on product differentiation rather than wheel reinvention.

While these are all benefits of high-quality SIP, designers have also learned that using poor SIP can have nasty consequences. Many pioneering IP users have stories of late development projects, unexpected and expensive silicon respins, and worse results from choosing bad SIP. It’s true that most providers of bad IP have now disappeared through natural selection in the marketplace, but it is unfortunately still possible to end up with a poor choice of SIP for your particular project. So yes, SIP quality is still very much an issue for most designs.

Efforts to objectively measure SIP quality go back to the early stages of SIP evolution. Attempts to set standards and metrics for the quality of SIP deliverables and verification—or at least to define best practices—include the Reuse Methodology Manual, VSIA’s QIP spreadsheet, and innumerable panel discussions and internal IP team debates.

Unfortunately, SIP design errors or bugs can still occur despite a high quality measure and a comprehensive verification plan. Choosing only proven and well-established SIP products helps. But past success does not guarantee an SIP block will be trouble-free in your particular system design: every use scenario and each new technology node present their own new challenges, problematic interdependencies between SoC building blocks can remain undetected until integration, and corner cases so far uncovered may suddenly make themselves known.

New quality challenges are also arising as the complexity of SoC designs increases and smooth SIP integration becomes essential. The portion of the development cycle spent on SIP integration is booming, and today, the SIP integration cost is typically a multiple of the SIP acquisition cost.

Because of this, savvy design teams have learned to look beyond the SIP itself and to consider the quality of the SIP provider and the effectiveness of their customer support. Rapid responses and access to the SIP’s actual developers—who are generally the best at quickly understanding and fixing your problems—can help save your project when problems somehow creep in.

Standardization of SoC bus or controller-PHY interfaces, new Verification IP, and packaging efforts like the XML tagging of IP-XACT, all effectively address the obvious connectivity problems, but this is only a part of the issue: once you connect your SIP and in-house blocks all together, they don’t necessarily work properly. SoC bus or memory bandwidth contention, un-matching throughputs, complex control factors, difficult-to-interface device drivers, software layers that drain host processor performance, and real-world signal integrity issues are just some of the challenges for today’s SoC designer.

To be considered “high quality” today, therefore, SIP must go beyond meeting functional requirements and also be designed for ease of integration from people that have experience and deep understanding of systems and applications.

One way SIP providers address this is by moving IP-based design a step further and offering pre-integrated SIP subsystems. Simple examples available now are controller-PHY-driver combos for most high-speed serial interfaces, and bridges between serial interfaces to memory controllers (e.g. USB to NAND-flash). Full processor-based SIP platforms are even available, ready for a designer’s customization through added hardware and differentiating software features. This trend also changes the focus of SIP vendor support from isolated application expertise to broader system design and integration issues. For example, data-intensive functions like video compression must work seamlessly with advanced memory devices or it doesn’t matter how well they do compression. Some SIP vendors are already going further and offering system integration services for their SIP products.

In conclusion, SIP quality does indeed still matter. But in today’s mature SIP marketplace—where most products comply with development and verification standards—new quality considerations relate to the ease and level of integration, as well as the support and integration services that are bundled with the SIP.

 

About Nikos Zervas

Nikos Zervas headshotNikos is the VP of Marketing for CAST, Inc. Before joining CAST in 2010, Nikos was a co-founder, chairman, and CEO of video/image SIP vendor Alma Technologies, SA. He has been a member of the board for the Hellenic Silicon Industry Association since 2009, and he is a senior member of IEEE. Nikos holds BA and PhD degrees in Electrical and Computer Engineering from the University of Patras, Greece, and has published over forty papers in referenced journals and international conferences

 

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