Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Secure Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs. See the video and image compression Family Page for a media compression overview.

 H.264 Video Decoders
Low Latency Constrained
  Baseline Profile

Low-Power Constrained
  Baseline Profile

 H.265 HEVC Decoders
Main Profile

Companion Cores
Image Processing
CAMFE Camera Processor
Network Stacks
40G UDPIP Stack
1G/10G UDPIP Stack
• Hardware RTP Stack
  – for H.264 Encoders
  – for H.264 Decoders
  – for JPEG Encoders
IEEE 802.1Qav & 802.1Qbv

• MPEG Transport Stream

JPEG Still & Motion

Lossless & Near-Lossless

Lossless Data Compression
GZIP Compressor
GUNZIP Decompressor
GZIP Reference Designs
    • for Intel FPGAs
    • for Xiinx FPGAs

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers

Device Controllers
smart card reader

Flash Controllers
Parallel Flash
Parallel Flash for AHB
Universal Serial NOR/NAND
   Flash for AHB

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

Octal/Quad/Dual/Single SPI
Quad SPI
Single SPI
SPI to AHB-Lite

Master/Slave Controller
Master  • Slave

These encryption cores make it easy to build security into a variety of systems.

GEON SoC Security
GEON Security

Encryption Primitives
AES, Programmable
Key Expander
Single, Triple

Hash Functions
SHA-3 (Keccak)

Other Posts & News

Recent Blog Posts

Recent News

See all the blog posts or news items

by CAST, Inc.

IoT Phase 2: Design Matters


by Bill FInch, SVP, CAST, Inc.

The next phase of the IoT is about to start. What most distinguishes it from the first? Clever design, using the right IP.

In the first phase, there was little clarity about what functionality really mattered. Engineers were tasked with getting products out ASAP. Because of the uncertainty and rush, early products were mostly built around off-the-shelf parts made by IDMs (Integrated Device Manufacturers). The emphasis was on getting things working under the new “IoT” umbrella, not on optimizing against more specific criteria.

This will not be true in the second phase.

In many markets, we will see a resurgence of custom SoCs being designed with a much clearer concept of what will differentiate these products from the competition. We always knew that power consumption in edge devices was a big deal, and now we know—with a great deal of certainty—what activities consume power. Optimizing to deal with these functions will now be paramount.

Clever design and using the right IP cores, are necessary for success in IoT Phase 2Wireless transmissions, no matter the frequency or standard, have to be optimized. There is, however, a limit to what can be done. Sooner or later you have to turn on the radio. Therefore, the best approach is to process the raw data at the source to reduce its size. This means far more compute power will be needed at the edge than most people originally believed.

More computing at the edge also means more software at the edge. More software means bigger memories, which then consume more power. So controlling the size of the on-board memories requires new thinking as well.

The PipelineZero approach to more efficient 32-bit processor architectureOne approach to meeting the challenge of optimizing power across the chip is to break the design down into sub-systems, each highly optimized for a particular function. Making this strategy work will require tiny processors that can each perform a single task very efficiently and then go to sleep immediately, once their job is done. Trying to force-fit a processor designed with the typical 32-bit architectures of pipelines and caches will not be good enough. (An excellent example of this new mindset is the BA20 “PipelineZero” 32-bit Processor.)

Another low-power approach is to optimize the video that many IoT applications capture, send, or display. Excellent codecs and hardware IP for video compression have been popular for years, but the IoT needs something different, not so much broadcast quality but rather good enough quality, but with very much use of power and silicon resources. Newer IP portfolios support this approach such as the latest generation of Video and Image IP Cores available from CAST.

JPEG & H.264 IP cores from CAST, Inc.Another way to reduce power and shrink the size of the main on-chip memories is to take a cue from the Data Center experts: use a data compression strategy. This is a well-known and proven technology.

By compressing the firmware when writing, decompressing, and reading, memory requirements can be substantially reduced and a significant amount of power can be saved. Unlike in the Data Center where processing power is abundant, when this technique is applied at the chip level it must be done with hardware accelerators. For a detailed example of how this works, see the conference paper Innovative Energy Savings Using GZIP IP Within IoT Devices.

Beyond technical issues, success in the second wave of the IoT requires that costs come down significantly. Well thought out designs that can achieve the kinds of economies of scale typically seen in consumer markets will be necessary for corporate success and profitability. Additionally, designing products that have a bill of materials with substantial built-in royalty streams will hold back success and lead to what in earlier generations was known as “profitless” prosperity: wildly successful products with margins so thin that no one made money.

Still, it remains to be seen whether the consolidation wave that has swept through the industry is going to lead to successful second-wave designs.

Most of the M&A of the past few years was focused on building products for smartphones and tablets and other leading edge consumer devices. These designs were giant multi-processor SoCs that required the latest bleeding edge process nodes to work. They required specialized design skills and large design teams. Today, however, such a hugely expensive infrastructure is not at all necessary to build many of the optimized IoT designs that define the second wave.

That is why it is highly likely we will see a return to the days when a few smart people with the right ideas can actually bring to market successful designs built on much cheaper processes. This might be the classic “two guys in a garage” using FPGAs or small start-up teams taking advantage of the latest tools and methods to produce more complex ASICs or SoCs. Being free of corporate structures that dictate choices in IP and tools will allow a more creative design approach and more cost effective—read “profitable”—IoT solutions.

Certainly one could ask, will funding be available? The answer depends on whether the Angels, the VCs and their brethren, can return to the days when they willingly took reasonable risks to fund people with a vision. The IoT will not be built on apps.

We’re not there yet, but the second wave of the IoT is coming. The time to prepare is now.



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