Digital IP Cores
and Subsystems

Our family of microcontroller and microprocessor related cores includes capable and competitive 32-bit BA22s and the best-available set of proven 8051s.

32-bit Processors
BA2x Family Overview

Secure Processors
Geon - Protected Execution

Application Processors
BA25 Adv. App. Processor
BA22 Basic App. Processor

Cache-Enabled Embedded
BA22 Cache-Embedded

Embedded Processors
BA22 Deeply Embedded
BA21 Low Power
BA20 PipelineZero

Processor-Based AMBA® Subsystems
Family Overview
AHB Low-Power
AHB Performance/Low-Power
AXI Custom Performance

AMBA Bus Infrastructure Cores
See Peripherals Cores >

Efficiently compress media or data with these high-performance hardware codecs. See the video and image compression Family Page for a media compression overview.

 H.264 Video Decoders
Low Latency Constrained
  Baseline Profile

Low-Power Constrained
  Baseline Profile

 H.265 HEVC Decoders
Main Profile

Companion Cores
Image Processing
WDR/HDR
CAMFE Camera Processor
Network Stacks
40G UDPIP Stack
1G/10G UDPIP Stack
• Hardware RTP Stack
  – for H.264
  – for JPEG
IEEE 802.1AS Time Sync.
   Stack

IEEE 802.1Qav & 802.1Qbv
   Stack

• MPEG Transport Stream
  Mux

JPEG Still & Motion
Encoders
Baseline
Extended
Ultra-Fast
Decoders
Baseline
Extended
Ultra-fast

JPEG-LS
Lossless & Near-Lossless
Encoder
Decoder

Lossless Data Compression
GZIP Compressor
GUNZIP Decompressor
GZIP Reference Designs
    • for Intel FPGAs
    • for Xiinx FPGAs

Easily integrate memories, peripherals, and hardware networking stacks into SoCs.

Display Controllers
TFT LCD

Device Controllers
smart card reader

Flash Controllers
Parallel Flash
Parallel Flash for AHB
Serial NOR/NAND Flash
Octal, XIP, DMA for AHB
Octal, XIP for AHB
Quad, XIP for AHB
Quad, XIP for AXI

Legacy Peripherals
DMA Controllers
8237, 82380
UARTs
16450S, 16550S, 16750S
Timer/Counter
8254

Quickly complete the standard parts of your SoC with these memory and peripheral controllers, interfaces, and interconnect cores.

SPI
Octal/Quad/Dual/Single SPI
XIP & DMA for AHB
XIP for AHB
Quad SPI
XIP & DMA for AHB
XIP for AHB
XIP for AXI
Master/Slave
Single SPI
Master/Slave
Bridges
SPI to AHB-Lite

I2C & SMBUS
Master/Slave Controller
Master/Slave VIP
I2C
Master  • Slave

These encryption cores make it easy to build security into a variety of systems.

AES
AES, programmable
  CCM, GCM, XTS
Key Expander

DES
DES single
DES triple

Hash Functions
SHA-3 (Keccak)
SHA-256
SHA-1
MD5

Other Posts & News

Recent Blog Posts

Recent News

See all the blog posts or news items

by CAST, Inc.

How To: Easily Control & Monitor Your Design Over Ethernet

Tech Note

Problem:

You’re developing a great SoC or FPGA design, and need an easy, equally great way to communicate with it from your PC.

The board does have an Ethernet port. But you don’t want to mess with embedded software networking stacks, because this might impact software performance, or maybe you don’t have processor cycles available to run it. Plus, your deadline is rapidly approaching and you really don’t need a whole new side project.

Solution:

Just connect our UDPIP core between the Ethernet MAC and your design, and easily implement a UDP-to-AXI-lite (or Avalon-MM) bridge.

The UDPIP-40G 40G UDP/IP Hardware Protocol Stack implements a UDP/IP hardware protocol stack that enables high-speed communication over a LAN or a point-to-point connection. Designed for standalone operation, the core is ideal for offloading the host processor from the demanding task of UDP/IP encapsulation and enables media streaming with speeds up to 40Gbps even in processor-less SoC designs.

With its optional NetCMD module, the UDP/IP core will “translate” UDP packets of special syntax to AXI-Lite (or Avalon-MM) read or write accesses in its AXI-Lite master port facing your design. For read accesses, the NetCMD module will return specially formed UDP packets containing the read data.

To make things simpler, NetCMD is delivered with a set of scripts and software utilities that form and parse the special UDP packets, and allow you to work with a simple text editor and a straightforward syntax (see the figure).

UDP/IP IP core integrated for easy system observation and control via Ethernet

System integration is equally easy: we will deliver a wrapper that integrates the UDP/IP core and the Ethernet MAC of your choice. (We have off-the-shelf wrappers for Altera and Xilinx eMACs, and we can put one in place for any other Ethernet MAC).

If you only need the eMAC or the UDP/IP core for communication, rest assured that they will not mess up your system design. You would just need to connect its control register interface to your bus, or if this seems difficult, we can hardwire its configuration for you.

The network configuration is also straightforward. The UDP/IP core implements DHCP, ARP,  so all you have to do is assign it an IP address in your network domain and you are done.

Our customers have been using this exact approach to simplify debugging or to enable run-time monitoring and control of their products in all kinds of designs, from Video Over IP devices, to simple IoT sensors. Learn more about this by visiting the UDPIP product page, email us or submit a Request Info form, or call any time (+1 201.391.8300).

 

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