USB IP Core USBHS-51_AP USB 2.0 High Speed Application Platform

On this page: Description | Applications | Features | Block Diagram | Debug Support | Options | Support | Verification | Deliverables

The USBHS-51_AP is a USB IF-certifiable hardware-software platform, enabling rapid development of USB 2.0 applications. It integrates a fast 8-bit microcontroller and a USB 2.0 High Speed controller, and it is accompanied with a powerful and comprehensive software stack.

The USBHS-51_AP retains all the configurable features of the CAST’s R8051XC2 microcontroller core.  It provides interrupts, interfaces for serial communication, timer system with compare-capture-reload resources, IO ports, power management unit, multiplication-division unit, DMA controller, watchdog timer and a real time clock. The rich set of peripherals included can be easily modified to satisfy any user application at minimum cost.

Applications

• USB Mass storage applications including  pen drives, hard drives, and memory card readers
  
• USB Audio/Video applications including cameras, video cameras, sound cards, TV tuners, audio processing consoles, and multimedia projectors
  
• Home Networking & Automation
• Personal Digital Assistants (PDA)
• USB Communication devices including modems, Ethernet cards, Bluetooth dongle, Wi-Fi dongle, and mobile phones
  
• Various computer peripheral devices including monitors, printers, scanners, keyboards, mouse and presenter pointers
• Digital Media Controllers including MP3 players, and portable video players

Features

• Integrates CAST cores and adds software stack:
• R8051XC2 8-bit microcontroller core
• USBHS-DEV Universal Serial Bus Peripheral Controller core
• USBFS-51_SS Software Stack

USBHS-DEV: USB 2.0 Peripheral Controller

• Hight and Full Speed operation according to USB 2.0 specification
  
• Optional protocol-aware DMA controller with configurable number of channels
  
• Up to 15 In and 15 Out endpoints

R8051XC2: 8-bit microcontroller

• Fully compatible with the MCS® 51 instruction set
  
• Single clock per cycle and efficient architecture for up to 12.1 times the performance of original 8051
  
• Fewer machine cycles means lower average power usage in most applications
  
• Extensive set of optional features and peripherals: choose configurable or less-expensive fixed versions
  
• EASE-8051 - KEIL™-compatible, complete application debugging environment

USBFS-51_SS: Software stack

• USB High/Full Speed specification compatible
  
• Complies with USB Command Verifier tests
  
• Highly portable embedded architecture / OS-independent
  
• Written in ANSI-C
  
• Small memory footprint

Block Diagram

Debug Support

Based on the R8051XC2 microcontroller core, the platform can be equipped with a complete debugging solution (EASE) which consists of:

• The On Chip Debug Support (OCDS) module built in the microcontroller core
• a USB-based Debug Pod for communication between the target IP core and the debugging software
• EDIk-51 software for interfacing with Keil μVision compiler/debugger

EASE helps SoC designers debug their applications by supporting:

• Standard debugging features (Code download, FLASH programming, Memory inspection, and Run/stop/step control)
• Optional debugging features including Program/Data Trace
• TCP/IP support for remote debugging

Options

• EDIF netlist for FPGA and low volume production
• Application-debugging Support Environment (EASE) that includes
• Debug hardware for R8051XC2 controller
• Software plug-in for Keil environment
• Dedicated USB pod for data exchange device between debug hardware and personal computer
• Evaluation system including:
• EB5-Tiny Development Board
• Implementation for Xilinx FPGA
• A PHY Extension board that meets the USB 2.0 Transceiver and Macrocell Tester (T&MT) Interface specification, and can be used to perform PHY interoperability testing for any USB transceiver
• R8051XC2 specific options:
• Pre-configured R8051XC2-A and -B versions
• Fully configurable version of R8051XC2 (R8051XC-F)

Support

The core as delivered is warranted against defects for ninety days from purchase. Thirty days of phone and email technical support are included, starting with the first interaction. Additional maintenance and support options are available.

Verification

All subcomponents were functionally verified with an HDL testbench using their individual test suites.

Deliverables

The core includes everything required for successful implementation:

• Verilog/VHDL source code or FPGA netlist
• Sophisticated Verilog 2001/VHDL Testbench
  
• Simulation script, vectors, expected results, and comparison utility
  
• Synthesis script (ASICs) or place and route script (FPGAs)
  
• Comprehensive user documentation, including detailed specifications and a system integration guide
  
• Complete C language source code set, example applications, documentation and integration guide for USBFS-51 Software Stack deliverables

On this page: Description | Applications | Features | Block Diagram | Debug Support | Options | Support | Verification | Deliverables

Download PDF datasheets for more info: ASIC

This core is sourced from the IP experts at Evatronix SA.